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Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors

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Abstract

In this work, with the help of extensive technology computer-aided design simulations, we report a comprehensive study of MOSFET based circuit design using ultra-thin body III-V on-insulator (OI) CMOS transistors. We demonstrate the circuit performance of III-V CMOS by combining InAs-OI n-channel and GaAs-OI junction-less p-channel transistors. The performance metrics of different circuits designed using III-V transistors are also compared with III-V/Germanium and Silicon-on-insulator (SOI) based CMOS logic. CMOS inverter circuit designed using III-V/Ge (InAs-OI/GeOI) CMOS shows 51% and 17% reduction in rise and fall time compared to SOI CMOS. The oscillation frequency of the ring oscillator designed using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) CMOS logic is approximately three times and two times higher than SOI based design. The unity-gain bandwidth of the inverting amplifier using III-V/Ge (InAs-OI/GeOI) and III-V (InAs-OI/GaAs-OI) architecture is 22 times and 9.5 times higher compared to SOI CMOS based circuit. Static noise margin (SNM) of conventional six-transistor (6-T) SRAM cell is also analyzed during hold operation. Due to the poor electrostatic integrity of III-V transistors, degradation in SNM is observed compared to its SOI counterparts. The cascode low noise amplifier (LNA) circuit designed using InAs-OI transistor shows the higher gain and low noise figure at the same operating frequency compared to the SOI transistor-based LNA.

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Acknowledgements

The second author thanks Department of Electronics and Information Technology, Govt. of India for utilizing the resources obtained under the SMDP-C2SD project at the University of Calcutta.

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  1. School of Electronics Engineering, Kalinga Institute of Industrial Technology (KIIT), Bhubaneswar, Odisha, Pin-751024, India

    Subir Kumar Maity

  2. Institute of Radio Physics and Electronics, University of Calcutta Kolkata, West Bengal, Pin-700009, India

    Soumya Pandit

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Correspondence to Subir Kumar Maity.

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Maity, S.K., Pandit, S. Performance Assessment of CMOS circuits using III-V on Insulator MOS Transistors. Silicon 13, 1939–1949 (2021). https://doi.org/10.1007/s12633-020-00582-3

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