Design of inductively degenerated common source RF CMOS Low Noise Amplifier

Abstract

The Low Noise Amplifier (LNA) is the first stage in RF CMOS receivers. The Common Gate (CG) LNA and Inductively Degenerated Common Source (CS) LNA are one of the widely used topologies for realizing RF CMOS receivers. The present work emphasizes a simple and exhaustive search procedure for the synthesis and analysis of CMOS CG and Inductively Degenerated CS LNA circuits. The width (W), gate source voltage ($V_{gs}$) and drain source voltage ($V_{ds}$) of the transistors constitute the design space in the circuit design. The design first involves the use of a circuit simulator (HSPICE) to obtain the small signal parameters of the circuit for various W, $V_{gs}$, and $V_{ds}$of the transistors and then to generate a Look-Up Table (LUT) for all design points using the obtained values. This LUT is used to meet the target performance specifications along with appropriate analytical expressions derived from the circuit in a numerical simulator (MATLAB). This will enable one to explore the whole design space quickly and fastly for arriving at the optimal values for the device dimensions, bias voltages and bias currents of the two LNA circuits. The design methodology is demonstrated by designing CG and Inductively Degenerated CS LNA circuits using 90 nm CMOS technology library in which Inductively Degenerated CS LNA gets high gain and low noise figure than CG LNA.