1 Introduction

MOSFET technology has played a very vital role in the continuous growth of semiconductor industry. By increasing the number of transistors on a single chip, the continuous scaling of the MOSFET transistor has degraded the device performance, which leads to high leakage current and severe short-channel effects (SCEs) [1, 2]. In this aspect, FinFET is a strong candidate, due to its excellent immunity against SCEs and its compatibility with the CMOS fabrication process [3, 4]. Various possibilities like modification of device architecture, channel/source material other than silicon, gate work function engineering, etc. were introduced by the researchers to improve the performance of FinFET. Many FinFET geometries such as double gate, triple gate, gate all around FinFET [5], pie gate FinFET [6], omega FinFET [7] and cylindrical FinFET [8] are reported in the literature. Moreover, to have high ON current, a heterojunction FinFET with Ge source is reported and its electrical properties for various fin dimensions are analysed [9]. Various electrical parameters such as transfer characteristic, output characteristic, switching ratio and subthreshold swing (SS) of high-k spacer junctionless FinFET (HKS JL-FinFET) are compared with conventional FinFET (C-FinFET) [10]. It is seen that HKS JL-FinFET performs better than C-FinFET. The DC and RF performances of JL-FinFET are studied for two different oxide thicknesses (\(t_{\mathrm {ox}}=0.4\) and 1 nm) and it is reported that device with \(t_{\mathrm {ox}}=1\) nm has improved cut-off frequency and unilateral gain compared to \(t_{\mathrm {ox}}=\) 0.4 nm [11]. For high power and mobility, a multichannel FinFET AlGaN/GaN high electron mobility transistor (HEMT) is optimised for various layer thicknesses, fin widths and channel doping concentrations [12]. Results reveal that FinFET with four channels has 3.2 times more transconductance than single channel device. The effect of \(\gamma \)-ray radiation on DC and RF parameters are reported with scaling of various device parameters such as gate length, number of fins and number of fingers in 10 nm n-FinFET [13]. The result reveals the \(\gamma \)-ray radiation degrades the maximum oscillation frequency, whereas cut-off frequency remains unchanged. The performance improvement and reduction in variability can be achieved through source/drain extension (SDE) in FinFET architecture and SDE doping is optimised to suppress the variability and enhance the \( I_{\mathrm {ON}}/I_{\mathrm {OFF}}\) ratio [14]. The RF parameters are suppressed and linearity figure of merits (FOMs) are improved in Fe-FinFET as temperature is increased, as pointed out by Saha et al [15].

On the other hand, reliability and applicability of the device for a wide variation in temperatures is a major concern and therefore, the effect of temperature and interface trap charges (ITC) have to be analysed. For the nanoscale device, the impact of interface trap charges present at the semiconductor and oxide interface is very prominent from the perspective of reliability. The interface trap fluctuation (ITF) with high-k/metal gate device demonstrated that ITF affects the device performance when it works in the strong inversion region [16]. The presence of ITC at the semiconductor and oxide interface reduces the electron mobility, which leads to a reduction in current [17].

Das and Baishya [18] have reported that the change in electrical characteristics in the presence of trap charges is negligible when heterodielectric BOX is considered instead of homodielectric BOX. Amoroso et al [19] reported that the impact of trap can be reduced by scaling down the fin dimensions and the applied gate voltage. Moreover, SRAM circuit implemented by FinFET has reduced statistical variation in read noise margin (RNM) and write noise margin (WNM) with increase in trap density [20]. The variability in threshold voltage is suppressed for NC-FinFET compared to conventional FinFET in the presence of interface trap density [21]. Likewise, the electrical characteristics of NC-Ge FinFET is improved with increased positive trap charges, whereas it degrades with negative trap charges [22]. Moreover, the effect of trap charge is very significant in tunnel FET (TFET) due to changes in the electric field induced by ITC. Madan and Chaujar [23] have demonstrated that the OFF-state of the device changes tremendously for the variation in trap charge densities. In [24], a comparative study of conventional SOI TFET, gate-on-source TFET and gate-on-source/channel TFET are investigated in the presence of trap charge. The analysis highlighted that gate-on-source/channel TFET has better immunity against the interface trap charge variation. It also exhibits higher ON current and ON to OFF current ratio than the other devices. The impact of interface trap charge on electrical parameters in NC-FinFET reveals that NC-FinFET is more resilient towards interface trap charge than the conventional FinFET [25].

In this paper, a heterojunction heterodielectric BOX (HJHDB) FinFET is proposed to reduce the effect of trap charge. The HJHDB FinFET can eliminate the effect of trap charge at various box thicknesses, temperatures and wide range of trap levels. Such effect of trap is demonstrated on various electrical parameters like transfer characteristics, surface potential, subthreshold swing and threshold voltage.

2 Device structure and TCAD deck

Fig. 1
figure 1

3D view of the FinFETs. (a) Heterojunction heterodielectric BOX (HJHDB) FinFET and (b) conventional FinFET.

Full size image

The 3D views of the heterojunction heterodielectric BOX (HJHDB) and conventional FinFETs (C-FinFETs) are shown in figures 1a and 1b, respectively. For HJHDB FinFET, the source region is made of germanium, whereas channel and drain regions are made of silicon; the high-k (HfO\(_{\mathrm {2}})\) dielectric material (\(k=\) 22) is considered as BOX under the drain region and the low-k (SiO\(_{\mathrm {2}})\) dielectric material (\(k=\) 3.9) is used as BOX for the remaining region. For C-FinFET, silicon and SiO\(_{\mathrm {2}}\) are considered as the fin material and the BOX, respectively. However, HfO\(_{\mathrm {2 }}\)and metal with work function (\(\Phi _{\mathrm {M}}=\) 4.4 eV) are considered as gate dielectric and gate material, respectively, for both the structures. A standard value of drain bias (\(V_{\mathrm {DS}}) =\) 0.5 V is considered. The n\(^{\mathrm {+ }}\)source/n\(^{\mathrm {+ }}\)drain regions are doped with concentration of 10\(^{\mathrm {19}}\) cm\(^{\mathrm {-3}}\) and the p-type channel region is doped with concentration of 10\(^{\mathrm {15}}\) cm\(^{\mathrm {-3}}\). The various device dimensions are: fin thickness (\(T_{\mathrm {fin}}) =\) 10 nm, fin height (\(H_{\mathrm {fin}}) =\) 20 nm, gate oxide thickness (\(t_{\mathrm {ox}}) =\) 1.5 nm, gate length (\(L) =\) 30 nm and the height of the BOX (\(t_{\mathrm {box}})\) is varied.

Fig. 2
figure 2

Effect of trap charges for different box height on transfer characteristics for (a) HJHDB and (b) C-FinFETs.

Full size image

All the simulations have been carried out using the TCAD Sentaurus simulator [26] and we have considered calibrated physics model during simulation as mentioned in our previous work [27]. The various physics models activated during simulations are: the carrier transport model used is a drift-diffusion model, which solves the Poisson’s and carrier transport equations; Fermi–Dirac statistics and Slootboom models are used to consider the highly doped source/drain region; Shockley–Read–Hall (SRH) model is activated for recombination of the carriers; to consider the mobility of the carriers the doping-dependent Masetti model with adjusted parameters is enabled in the simulator. In this work, interface trap charge (ITC) is considered at the interface of Si–HfO\(_{\mathrm {2}}\) in the channel region of 10\(^{\mathrm {12}}\) cm\(^{\mathrm {-3 }}\)trap density according to the published data [28]. However, to analyse the effect of trap variations, the trap density is varied from 10\(^{\mathrm {11}}\) to 10\(^{\mathrm {13}}\) cm\(^{\mathrm {-3}}\). The distribution of the trap charge density is considered uniform for the entire simulations.

3 Results and discussion

3.1 Effect of BOX height

The effect of interface trap charge on transfer characteristics for both the HJHDB and C-FinFETs are shown in figures 2a and 2b, respectively. The increase in box height enhances the channel potential, which results in the high value of ON current for both devices. As expected, the ON current reduces in the presence of trap charges (figure 2). It is seen from figure 2a that the effect of trap is insignificant in HJHDB compared to the conventional device and this is due to the presence of high-k BOX under the drain region. This high-k BOX eliminates the depletion region under the channel–drain interface and accordingly, the trap effect gets nullified [29]. It can be better explained from figure 3, which shows the effect of trap charges on the channel potential for both the devices. It is seen that there is no effect of trap charges for HJHDB FinFET, whereas the potential of C-FinFET is significantly affected by trap charge.

The effects of trap charges on SS and threshold voltage taking box thickness as a parameter are portrayed in figures 4a and 4b, respectively. As box height increases, the leakage current decreases, which leads to a decrease in SS values for both the devices as summarised in figure 4a. As expected, the effect of trap on SS value is insignificant for HJHDB FinFET, whereas trap effect is prominent for C-FinFET. The threshold voltage of the devices is measured at a constant current of 10\(^{\mathrm {-7}}\) A, and ON current increases with box thickness, which correspond to an increase in threshold voltage as shown in figure 4b. It is also observed that the effect of trap charges is significant for C-FinFET and such effect is not observed for HJHDB FinFET.

Fig. 3
figure 3

Effect of trap charges on potential for both HJHDB and C-FinFETs when \(t_{\mathrm {box}}=\) 40 nm.

Full size image
Fig. 4
figure 4

Effect of trap charges on (a) SS vs. box height and (b) threshold voltage vs. box height for both HJHDB and C-FinFETs.

Full size image

3.2 Effect of temperature

Fig. 5
figure 5

Effect of trap charges for different temperature on transfer characteristics for (a) HJHDB and (b) C-FinFETs when \(t_{\mathrm {box}}=40\) nm.

Full size image

The effect of temperature in the presence of trap charges for both the devices is studied by plotting the transfer characteristics as shown in figure 5. It is seen that the effect of temperature is very prominent for both the devices. However, even at high temperature, the impact of trap charge is negligible in HJHDB FinFET. At high gate voltage, the mobility of the carriers reduces, which leads to a decrease in ON current. However, at low gate voltage, energy band gap reduces with increased temperature which results in an increase in OFF current. Again, the effect of trap charge on the potential for HFHDB and C-FinFETs are shown in figures 6a and 6b, respectively. It is observed from the potential plot that the effect of trap charge is absent in HJHDB at high temperature (figure 6a), whereas this effect is prominent in C-FinFET (figure 6b).

Fig. 6
figure 6

Effect of trap charges for different temperature on potential for (a) HJHDB and (b) C-FinFETs when \(t_{\mathrm {box}}=40\) nm.

Full size image

The effects of temperature on SS and threshold voltage in the presence of trap charges for both the devices are shown in figures 7a and 7b, respectively. It is visualised from figure 7 that, both SS and threshold voltage are significantly affected by temperature. However, the impact of trap charge is negligible for HJHDB FinFET at higher temperature as well. SS is directly related to the temperature [30], which in turn degrades the SS value with increase in temperature. It is seen that threshold voltage reduces with the rise in temperature and this is due to the degradation in OFF current with the rise in temperature as shown in figure 7b.

Fig. 7
figure 7

Effect of trap charges on (a) SS vs. temperature and (b) threshold voltage vs. temperature for both HJHDB and C-FinFETs when \(t_{\mathrm {box}}=40\) nm.

Full size image

3.3 Effect of trap level

The impact of trap level on HJHDB and C-FinFETs are shown in figures 8a and 8b, respectively, for both linear and log scale. It is seen that the increase in trap level decreases the ON current for both the devices. The increase in trap level increases the flat band voltage and consequently, the drain current is affected significantly in the superthreshold regime. On the other hand, the effect of trap level is very insignificant for HJHDB FinFET (figure 8a) compared to C-FinFET due to the presence of high-k box under the drain region.

Fig. 8
figure 8

Effect of different trap levels on transfer characteristics for (a) HJHDB and (b) C-FinFETs.

Full size image
Fig. 9
figure 9

Effect of trap level on potential for (a) HJHDB and (b) C-FinFETs.

Full size image

The effect of trap level on surface potential for HJHDB and C-FinFETs are shown in figures 9a and 9b, respectively. It can be seen that the changes in potential is negligible as the trap level concentration changes in HJHDB FinFET, whereas in C-FinFET, the potential changes by an observable amount. This behaviour in potential for HJHDB FinFET indicates insignificant changes in drain current as shown in figure 8a.

Fig. 10
figure 10

Effect of trap level on (a) SS and (b) threshold voltage for both HJHDB and C-FinFETs.

Full size image

The impact of trap charge on SS and threshold voltage for both HJHDB and C-FinFETs are reported in figures 10a and 10b, respectively. It is seen from figure 10a, that there is an insignificant change in SS for HJHDB FinFET with trap level. However, SS reduces for C-FinFET with increase in trap density \( N_{\mathrm {f}}\) and this is due to a decrease in drain current in the subthreshold region. It is also observed from figure 10b that, the threshold voltage increases with rise in \(N_{\mathrm {f}}\) and this is because of reduction in drain current with \(N_{\mathrm {f}}\), as observed in figure 8.

4 Conclusions

In this work, the reliability issues of HJHDB FinFET is presented by varying the BOX thickness and temperature in the presence of fixed trap charge. The performance of this device is compared with C-FinFET using TCAD simulator. By varying BOX thickness, there is no effect of the trap on drain current, SS and threshold voltage for HJHDB, whereas such electrical parameters of C-FinFET is affected by tarp charge. It has been shown that the proposed device has a negligible impact of trap charge at high temperature compared to C-FinFET. Furthermore, the effects of trap level on drain current and short channel characteristic are observed for both the devices. It is seen that the electrical parameters of HJHDB FinFET are more immune to trap level variation than C-FinFET. Therefore, HJHDB FinFET is a reliable device for wide variations of BOX thickness, temperature, trap level and it can be a promising candidate for low power applications.