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Impact of Noise and Interface Trap Charge on a Heterojunction Dual-Gate Vertical TFET Device

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Abstract

Herein, a vertical T-shaped heterojunction tunnel field-effect transistor (TFET) structure is proposed. This paper explores the effect of the traps and noise on the electrical characteristics. TFET devices work on the principle of band-to-band tunneling (BTBT). In order to increase the BTBT rate, the proposed structure uses an InP/In0.47Ga0.53 as the heterojunction at the source. In addition, this structure has dual metal gates: gate 1 with a 4.3 eV work function and gate 2 with a 4.1 eV work function. The effect of noise on device performance is investigated in terms of the voltage noise spectral density (Svg) and current noise spectral density (Sid), and the noise spectral densities are compared in the presence of interface trap concentrations. Finally, the variation in noise density with frequency is examined.

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Acknowledgments

This work was supported by the NIT, Silchar.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, Assam, 788010, India

    Karthik Nasani, Brinda Bhowmick & Puspa Devi Pukhrambam

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  1. Karthik Nasani
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  2. Brinda Bhowmick
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  3. Puspa Devi Pukhrambam
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Correspondence to Karthik Nasani.

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Nasani, K., Bhowmick, B. & Pukhrambam, P.D. Impact of Noise and Interface Trap Charge on a Heterojunction Dual-Gate Vertical TFET Device. J. Electron. Mater. 53, 2181–2190 (2024). https://doi.org/10.1007/s11664-024-10927-y

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