Abstract
This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiO x -cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in I D–V G characteristics is presented after the ‘Write’ cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II–VI layer as the gate insulator.
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F. Jain, S. Karmakar, P.-Y. Chan, E. Suarez, M. Gogna, J. Chandy, and E. Heller, J. Electron. Mater. 41, 2780 (2012).
J. Kondo, M. Lingalugari, P.-Y. Chan, E. Heller, and F. Jain, Proceedings of TechConnect World 2013 (Washington, D.C., 2013).
F.C. Jain and F. Papadimitrakopoulos, US Patent 7, 368, 370, (2008).
M. Gogna, E. Suarez, P.-Y. Chan, F. Al-Amoody, S. Kamakar, and F. Jain, J. Electron. Mater. 40, 1769 (2011).
F. Jain, P.-Y. Chan, E. Suarez, M. Lingalugari, J. Kondo, P. Gogna, B. Miller, J. Chandy, and E. Heller, J. Electron. Mater. 42, 3191 (2013).
F.C. Jain, E. Suarez, M. Gogna, F. Alamoody, D. Butkiewicus, R. Hohner, T. Liaskas, S. Karmakar, P.-Y. Chan, B. Miller, J. Chandy, and E. Heller, J. Electron. Mater. 38, 1574 (2009).
R. Velampatiand and F.C. Jain, NSTI Nanotech (Santa Clara, CA, May 20–24, 2007).
E.-S. Hasaneen, E. Heller, R. Bansal, and F. Jain, Solid State Electron. 48, 2055 (2004).
P.-Y. Chan, M. Gogna, E. Suarez, S. Karmakar, F. Al-Amoody, B.I. Miller, and F.C. Jain, J. Electron. Mater. 40, 1685 (2011).
P.-Y. Chan, E. Suarez, M. Gogna, B.I. Miller, E.K. Heller, J.E. Ayers, and F.C. Jain, J. Electron. Mater. 41, 2810 (2012).
P.-Y. Chan, M. Gogna, E. Suarez, F. Al-Amoody, S. Karmakar, B.I. Miller, E.K. Heller, J.E. Ayers, and F.C. Jain, J. Electron. Mater. 42, 3259 (2013).
J. Chandy and F. Jain. Proceeding to International Symposium on Multiple Valued Logic (Dallas, Texas, 2008), p. 186.
T. Hanyu and M. Kameyama, IEEE J. Solid State Circ. 30, 1239 (1995).
A.F. Gonzalez and P. Mazumder, IEEE Trans. Comput. 47, 947 (1998).
B. Radanovic and M. Syrzycki, Canadian Conference on Electrical and Computer Engineering, (1996), p. 190.
O. Ishizuka and D. Handoko, Proceeding 27th International Symposium Multiple-Valued Logic, (1997), p. 169.
T. Okuda and T. Murotani, IEEE J. Solid State Circ. 32, 1743 (1997).
X. Sun, S. Cui, A. Alian, G. Brammertz, C. Merckling, D. Lin, and T.P. Ma, IEEE Electron Device Lett. 33, 438 (2012).
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Kondo, J., Lingalugari, M., Chan, PY. et al. Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells. J. Electron. Mater. 44, 3188–3193 (2015). https://doi.org/10.1007/s11664-015-3895-1
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DOI: https://doi.org/10.1007/s11664-015-3895-1