Conclusion
In this study, we propose a co-optimization method of array operation and weight mapping for flash computing arrays to improve computing efficiency and accuracy. The proposed co-optimization can minimize the required computing periods to improve computing efficiency and can maximally decrease the IBLs to alleviate the impact of interconnect resistance. The results show the computing speed is improved by 2x and the accuracy loss induced by the interconnect resistance is maximally reduced to 62%, compared to the conventional method.
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Acknowledgements
This work was supported by National Key Research and Development (Grant Nos. 2018YFE0100800, 2019YFB2205100), National Nature Science Foundation of China (Grant No. 61841404), and the 111 project (Grant No. B18001).
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Yu, G., Huang, P., Han, R. et al. Co-optimization strategy between array operation and weight mapping for flash computing arrays to achieve high computing efficiency and accuracy. Sci. China Inf. Sci. 66, 129403 (2023). https://doi.org/10.1007/s11432-021-3381-3
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DOI: https://doi.org/10.1007/s11432-021-3381-3