Abstract
With its advantages in wirelength reduction and routing flexibility compared with conventional Manhattan routing, X architecture has been proposed and applied to modern IC design. As a critical part in high-performance integrated circuits, clock network design meets great challenges due to feature size decrease and clock frequency increase. In order to eliminate the delay and attenuation of clock signal introduced by the vias, and to make it more tolerant to process variations, in this paper, we propose an algorithm of a single layer zero skew clock routing in X architecture (called Planar-CRX). Our Planar-CRX method integrates the extended deferred-merge embedding algorithm (DME-X, which extends the DME algorithm to X architecture) with modified Ohtsuki’s line-search algorithm to minimize the total wirelength and the bends. Compared with planar clock routing in the Manhattan plane, our method achieves a reduction of 6.81% in total wirelength on average and gets the resultant clock tree with fewer bends. Experimental results also indicate that our solution can be comparable with previous non-planar zero skew clock routing algorithm.
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Supported in part by the National Natural Science Foundation of China (Grant No. 60876026), and the Specialized Research Fund for the Doctoral Program of Higher Education (Crant No. 200800030026)
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Shen, W., Cai, Y., Hong, X. et al. A single layer zero skew clock routing in X architecture. Sci. China Ser. F-Inf. Sci. 52, 1466–1475 (2009). https://doi.org/10.1007/s11432-009-0028-6
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DOI: https://doi.org/10.1007/s11432-009-0028-6