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Algorithmic aspects of area-efficient hardware/software partitioning

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Abstract

Area efficiency is one of the major considerations in constraint aware hardware/software partitioning process. This paper focuses on the algorithmic aspects for hardware/software partitioning with the objective of minimizing area utilization under the constraints of execution time and power consumption. An efficient heuristic algorithm running in O(n log n) is proposed by extending the method devised for solving the 0-1 knapsack problem. Also, an exact algorithm based on dynamic programming is proposed to produce the optimal solution for small-sized problems. Simulation results show that the proposed heuristic algorithm yields very good approximate solutions while dramatically reducing the execution time.

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Authors and Affiliations

  1. Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore, 639798

    Wu Jigang & Thambipillai Srikanthan

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  1. Wu Jigang
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  2. Thambipillai Srikanthan
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Correspondence to Wu Jigang.

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Jigang, W., Srikanthan, T. Algorithmic aspects of area-efficient hardware/software partitioning. J Supercomput 38, 223–235 (2006). https://doi.org/10.1007/s11227-006-8045-3

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