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Adaptive Bayesian Diagnosis of Intermittent Faults

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Abstract

With increasing transient error rates, distinguishing intermittent and transient faults is especially challenging. In addition to particle strikes relatively high transient error rates are observed in architectures for opportunistic computing and in technologies under high variations. This paper presents a method to classify faults into permanent, intermittent and transient faults based on some intermediate signatures during embedded test or built-in self-test.

Permanent faults are easily determined by repeating test sessions. Intermittent and transient faults can be identified by the amount of failing test sessions in many cases. For the remaining faults, a Bayesian classification technique has been developed which is applicable to large digital circuits. The combination of these methods is able to identify intermittent faults with a probability of more than 98 %.

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References

  1. Agosta JM, Gardos T (2004) Bayes network “smart” diagnostics”. Intel Techno J 8(4)

  2. Amgalan U, Hachmann C, Hellebrand S, Wunderlich H-J (2008) “Signature rollback - a technique for testing robust circuits”, proceedings IEEE VLSI test symposium (VTS’08). San Diego, California, pp 125–130

    Google Scholar 

  3. Aminian F, Aminian M (2001) Fault diagnosis of analog circuits using Bayesian neural networks with wavelet transform as preprocessor”. J Electron Test (JETTA) 17(1):29–36

    Article  Google Scholar 

  4. Barber D (2012) Bayesian reasoning and machine learning”. Cambridge University Press, New York

    Google Scholar 

  5. Bardell PH, McAnney WH (1982) “Self-Testing of Multichip Logic Modules”, Proceedings IEEE Int. Test Conference (ITC’82), Philadelphia, PA, USA, pp 200–204

  6. Barford L, Kanevsky V, Kamas L (2004) “Bayesian fault diagnosis in large-scale measurement systems”, Proceedings IEEE Instrumentation and Measurement Technology Conference (IMTC’04), Como, Italy, Vol. 2, pp 1234–1239

  7. Baumann R (2005) Soft errors in advanced computer systems”. IEEE Design & Test of Comput 22(3):258–266

    Article  Google Scholar 

  8. Ben-Gal I (2007) “Bayesian Networks”, in Ruggeri F, Faltin F, Kenett R, “Encyclopedia of Statistics in Quality & Reliability”, Wiley & Sons

  9. Borkar S (2005) Designing reliable systems from unreliable components: the challenges of transistor variability and degradation”. IEEE Micro 25(11):10–16

    Article  Google Scholar 

  10. Brglez F et al (1985) “Accelerated ATPG and fault grading via testability analysis”, proceedings IEEE international symposium on circuits and systems (ISCAS’85). Kyoto, Japan, pp 695–698

    Google Scholar 

  11. Cheng W-T, Sharma M, Rinderknecht T, Lai L, Hill C (2006) “Signature based diagnosis for logic BIST”, Proceedings IEEE Int. Test Conference (ITC’06), Santa Clara, CA, USA, pp 1–9

  12. Constantinescu C (2003) Trends and challenges in VLSI circuit reliability”. IEEE Micro 23(4):14–19

    Article  Google Scholar 

  13. Cook A, Elm M, Wunderlich H-J, Abelein U (2011) “Structural in-field diagnosis for random logic circuits”, proceedings european test symposium (ETS’11). Trondheim, Norway, pp 111–116

    Google Scholar 

  14. Cook A, Hellebrand S, Indlekofer T, Wunderlich H-J (2011) “Diagnostic test of robust circuits”, proceedings Asian test symposium (ATS’11). New Delhi, India, pp 285–290

    Google Scholar 

  15. Cook A, Wunderlich H-J (2014) “Diagnosis of multiple faults with highly compacted test responses”, proceedings 19th IEEE european test symposium (ETS'14). Paderborn, Germany, pp 1–6

    Google Scholar 

  16. De Kleer J (2009) “Diagnosing multiple persistent and intermittent faults”, proceedings 21st international joint conference on artificial intelligence (IJCAI'09). Pasadena, California, pp 733–738

    Google Scholar 

  17. Elm M, Wunderlich H-J (2010) “BISD: scan-based built-in self-diagnosis”, proceedings design automation and test in Europe (DATE’10). Dresden, Germany, pp 1243–1448

    Google Scholar 

  18. Ernst D et al (2004) Razor: circuit-level correction of timing errors for Low power operation”. IEEE Micro 24(6):10–20

    Article  MathSciNet  Google Scholar 

  19. Fechner B (2008) “A dynamic fault classification scheme”, proceedings european safety and reliability conference (ESREL’08). Valencia, Spain, pp 147–153

    Google Scholar 

  20. Ghosh-Dastidar J, Touba NA (2000) “A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains”, proceedings 18th IEEE VLSI test symposium (VTS’00). Montreal, Canada, pp 79–85

    Google Scholar 

  21. Gupta P, Agarwal Y, Dolecek L, Dutt N, Gupta RK, Kumar R, Mitra S, Nicolau A, Rosing TS, Srivastava MB, Swanson S, Sylvester D (2013) Underdesigned and opportunistic computing in presence of hardware variability”. IEEE Trans Computer-Aided Design of Integr Circ Syst 32(1):8–23

    Article  Google Scholar 

  22. Holst S, Wunderlich H-J (2009) Adaptive debug and diagnosis without fault dictionaries”. J Electronic Testing (JETTA) 25(4–5):259–268

    Article  Google Scholar 

  23. Indlekofer T, Schnittger M, Hellebrand S (2010) “Efficient Test Response Compaction for Robust BIST Using Parity Sequences”, Proceedings 28th IEEE Int. Conference on Computer Design (ICCD’10), Amsterdam, The Netherlands, pp 480–485

  24. Krishnan S, Doornbos KD, Brand R, Kerkhoff HG (2010) “Block-level Bayesian diagnosis of analogue electronic circuits”, proceeding design, automation and test in Europe (DATE'10). Dresden, Germany, pp 1–6

    Google Scholar 

  25. Liu C, Chakrabarty K, Goessel M (2002) “An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST environment”, proceedings design, automation and test in Europe (DATE’02). France, Paris, pp 382–386

    Google Scholar 

  26. Liu F, Nikolov PK, Ozev S (2006) “Parametric fault diagnosis for analog circuits using a Bayesian framework”, proceedings 24th IEEE VLSI test symposium (VTS’06). CA, USA, Berkeley, pp 272–277

    Google Scholar 

  27. Nicolaidis M (1999) “Time redundancy based soft-error tolerant circuits to rescue very deep submicron”, proceedings 17th IEEE VLSI test symposium. San Diego, CA, USA, pp 86–94

    Google Scholar 

  28. Nicolaidis M (2007) “GRAAL: a New fault tolerant design paradigm for mitigating the flaws of deep nanometric designs”, proceedings IEEE international test conference (ITC’07). CA, USA, San Jose, pp 1–10

    Google Scholar 

  29. O’Farrill C, Moakil-Chbany M, Eklow B (2005) “Optimized reasoning-based diagnosis for non-random, board-level, production defects”, proceedings IEEE international test conference (ITC’05). Austin, Texas, pp 173–179

    Google Scholar 

  30. Pearl J (1988) “Probabilistic reasoning in intelligent systems: networks of plausible inference”, revised 2nd printing. Morgan Kaufmann Publishers, San Francisco

    Google Scholar 

  31. Polian I, Czutro A, Kundu S, Becker B (2007) Power droop testing”. IEEE Design & Test of Computers 24(3):276–284

    Article  Google Scholar 

  32. Przytula KW, Thompson D (2000) “Construction of Bayesian networks for diagnostics”, Proceedings 2000 I.E. Aerospace Conference, Big Sky, MT, USA, Vol. 5, pp 193–200

  33. Rajski J, Tyszer J (1999) Diagnosis of scan cells in BIST environment”. IEEE Trans Computers 48(7):724–731

    Article  MathSciNet  Google Scholar 

  34. Tang H, Manish S, Rajski J, Keim M, Benware B (2007) “Analyzing volume diagnosis results with statistical learning for yield improvement”, proceeding 12th IEEE european test symposium (ETS’07). Freiburg, Germany, pp 145–150

    Google Scholar 

  35. Tirumurti C, Kundu S, Sur-Kolay S, Chang Y-S (2004) “A modeling approach for addressing power supply switching noise related failures of integrated circuits”, proceedings design, automation and test in Europe (DATE’04). France, Paris, pp 1078–1083

    Google Scholar 

  36. Wang S, Wei W (2009) “Machine learning-based volume diagnosis”, proceedings design, automation and test in Europe (DATE'09). Nice, France, pp 902–905

    Google Scholar 

  37. Wohl P, Waicukauski JA, Patel S, Maston G (2002) “Effective diagnostics through interval unloads in a BIST environment”, proceedings 39th design automation conference (DAC’02). New Orleans, Los Angeles, pp 249–254

    Google Scholar 

  38. Ye B, Luo Z, Zhang W, Piao C (2008) “Fault diagnosis for power circuits based on SVM within the Bayesian framework”, proceedings world congress on intelligent control and automation (WCICA’08). Chongqing, China, pp 5125–5129

    Google Scholar 

  39. Zhang Z, Wang Z, Gu X, Chakrabarty K (2010) “Board-level fault diagnosis using Bayesian inference”, proceedings 28th IEEE VLSI test symposium (VTS’10). Santa Cruz, California, pp 244–249

    Google Scholar 

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Authors and Affiliations

  1. Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Pfaffenwaldring 47, 70569, Stuttgart, Germany

    Laura Rodríguez Gómez, Alejandro Cook & Hans-Joachim Wunderlich

  2. Institute of Electrical Engineering and Information Technology, University of Paderborn, Warburger Straße 100, 33098, Paderborn, Germany

    Thomas Indlekofer & Sybille Hellebrand

Authors
  1. Laura Rodríguez Gómez
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  2. Alejandro Cook
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  3. Thomas Indlekofer
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  4. Sybille Hellebrand
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  5. Hans-Joachim Wunderlich
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Correspondence to Sybille Hellebrand.

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Responsible Editor: L. M. Bolzani Pöhls

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Gómez, L.R., Cook, A., Indlekofer, T. et al. Adaptive Bayesian Diagnosis of Intermittent Faults. J Electron Test 30, 527–540 (2014). https://doi.org/10.1007/s10836-014-5477-1

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  • DOI: https://doi.org/10.1007/s10836-014-5477-1

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