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Scan Test Response Compaction Combined with Diagnosis Capabilities

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Abstract

As today’s process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.

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Notes

  1. Our experience is that by following standard DFT rules (e.g. full-scan, shadow multiplexers behind memory blocks, no tri-state busses), ‘X’ densities in the range 0.001% to 0.005% are typically observed. In our design flow we use a in-house utility called ‘Xtract’ to analyse the ‘X’ contents in scan test response data. See also [15], where the authors characterize an ‘X’ density of 0.15% as “poor” and an ‘X’ density of 0.02% as “fair”.

References

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Authors and Affiliations

  1. Nordic Semiconductor ASA, Trondheim, Norway

    Sverre Wichlund & Frank Berntsen

  2. Norwegian University of Science and Technology, Trondheim, Norway

    Einar Johan Aas

Authors
  1. Sverre Wichlund
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  2. Frank Berntsen
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  3. Einar Johan Aas
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Correspondence to Sverre Wichlund.

Additional information

Responsible Editor: N. A. Touba

Appendix

Appendix

1.1 Proofs

Proof sketches for propositions 1–6 are presented below. Some of the proofs are based on induction, given the recursive nature of the design as shown in Fig. 3.

Proof of proposition 1

A single error appearing on an odd numbered input will appear on just one output of any bottommost building block in the main tree, see Fig. 2. From this output it will propagate to an output of an aux tree and/or the main tree.

A single error on an even numbered input will appear on both outputs on a bottommost building block in the main tree. However these outputs will never cancel since the only fan-out is within a building block, and the two outputs of a building block will never reconverge.

From the structure of the main tree, it is obvious that the error will appear on the Y and Y′ outputs within the next t cycles as well.

Proof of proposition 2

It is easily shown that this proposition holds for N = 8 (t = 3). Assume that the proposition holds for N = 2t where t > 3. Then it must hold for N = 2(t+1) as well; if both errors appear on the inputs of one of the N-compactors in Fig. 3, then by the assumption it will manifest itself on this compactor’s outputs in the same or at a later cycle. Since the outputs from this compactor don’t reconverge, it follows that the error will manifest itself on the outputs of the 2N-compactor in the same or at a later cycle.

If one error appear on each of the two N-compactor’s inputs, then it follows by proposition 1 and the properties of the building block, that the error will manifest itself on the outputs of the 2N-compactor in the same or at a later cycle.

Proof of proposition 3

It is easily shown that this proposition holds for N = 8 (t = 3). Assume that the proposition holds for N = 2t where t > 3. Then it must hold for N = 2(t+1) as well; if the single-error and the unknown (‘X’) appear on the inputs of one of the N-compactors in Fig. 3, then by the assumption it will manifest itself on this compactor’s outputs in the same or at a later cycle. Since the outputs from this compactor don’t reconverge, it follows that the error can’t be masked by any ‘X’, and thus will manifest itself on the outputs of the 2N-compactor in the same or at a later cycle.

If the single-error appears on one of the N-compactor’s inputs and the unknown on the other, then it follows by proposition 1 and the properties of the building block, that the error will manifest itself on the outputs of the 2N-compactor in the same or at a later cycle.

Proof of proposition 4

It is relatively easy to show that this proposition holds for N = 4 (t = 2). Assume that the proposition holds for N = 2t where t > 2. Then it must hold for N = 2(t+1) as well; if two errors enter one of the N-compactors in Fig. 3, and the unknown (‘X’) the other, then two cycles with an error, but only one cycle with an ‘X’ will enter the inputs of the basic block in the 2N-compactor. Thus the error will be detected.

If one error enters one of the N-compactors in Fig. 3, and the other error plus the unknown (‘X’) enter the other N-compactor, then at least one cycle with an error, but just one cycle with an ‘X’ will enter the inputs of the basic block in the 2N-compactor. Thus the error will be detected.

Proof of proposition 5

The output of a given tree (main/aux) in the compactor, computes the XOR of all input variables, some of them delayed in time 1,...,t cycles.

Assume that an odd number of errors enter the compactor inputs in a given cycle. This is equivalent to removing the flip-flops from the XOR trees and instead spacing the number of errors in time accordingly. Thus for a given cycle, if an odd number of errors enter the compactor, error detection is accomplished. Furthermore, such a cycle will exist, since an odd number cannot be the sum of only even numbers.

Proof of proposition 6

It is easily shown that this proposition holds for N = 8 (t = 3). Assume that the proposition holds for N = 2t where t > 3. Then it must hold for N = 2(t+1) as well. If the single-error appears on the uppermost N-compactor’s inputs, then by the structure of the basic block it will manifest itself on the Y and Y′ outputs of the 2N-compactor in the same cycle.

If the single-error appears on the bottommost N-compactor’s inputs, then it will manifest itself on the Y output of the 2N-compactor in the same cycle and on the Y′ output of the 2N-compactor in the next cycle.

By the assumptions, the other outputs of the N-compactors are without any loss of information provided as auxiliary outputs to the 2N-compactor, thus providing the diagnostic information within one N-compactor.

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Wichlund, S., Berntsen, F. & Aas, E.J. Scan Test Response Compaction Combined with Diagnosis Capabilities. J Electron Test 24, 235–246 (2008). https://doi.org/10.1007/s10836-007-5043-1

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