Skip to main content

Advertisement

SpringerLink
Log in

Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

Present complementary metal–oxide–semiconductor (CMOS) technology with scaled channel lengths exhibits higher energy consumption in designing secure electronic circuits against hardware vulnerabilities and breaches. Specifically, CMOS sense amplifier-based secure differential power analysis (DPA) countermeasures at scaled channel lengths show large energy consumption, with increased vulnerability. Additionally, spin-transfer torque magnetic tunnel junction (STT-MTJ) and CMOS-based logic-in-memory (LiM) cells demonstrate high energy consumption due to the large write current requirement of the STT-MTJ and poor MOS device performance at scaled channel lengths. This paper for the first time leverages emerging tunnel field effect transistor (TFET) steep-slope device characteristics and compatible non-volatile STT-MTJ devices for enhanced hardware security with ultra-low energy consumption at lower supply voltages. TFET-based sense amplifier-based logic (SABL) gates are proposed that achieve 3× lower energy consumption than the Si FinFET SABL designs. Further, utilizing TFET SABL gates, a TFET PRIDE S-box is designed that exhibits higher DPA resilience with 3.2× lower energy consumption than the FinFET designs. With the resulting lower static power consumption, TFET SABL-based cryptosystems are thus less vulnerable to static power side-channel attacks. Additionally, the proposed STT-MTJ and TFET LiM gates achieve 4× lower energy consumption than the STT-MTJ and FinFET designs. Lastly, these gates are explored in a logic encryption/locking technique that shows 3.1× lower energy consumption than the STT-MTJ and FinFET-based design.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Data availability

Enquiries about data availability should be directed to the authors.

References

  1. Li, A., Shinde, Y., Shi, J., Ye, X., Li, Y., Song, W.Z.: System statistics learning-based IoT security: feasibility and suitability. IEEE J Internet Things. 6(4), 6396–6403 (2019)

    Article  Google Scholar 

  2. The cost of malicious cyber activity to the US economy, W. House, 2018. [Online]. Available:https://www.whitehouse.gov/wpcontent/uploads/2018/03/The-Cost-of-Malicious-Cyber-Activity-to-the-U.S.-Economy.pdf

  3. Bartock, M., Souppaya, M., Savino, R., Knoll, T., Shetty, U., Cherfaoui, M., Yeluri, R. and Scarfone, K.: Hardware-enabled security for server platforms: enabling a layered approach to platform security for cloud and edge computing use cases. National Institute of Standards and Technology. (pp. 39–39)

  4. Roshanisefat, S., Kamali, H.M., Homayoun, H., Sasan, A.: SAT-hard cyclic logic obfuscation for protecting the IP in the manufacturing supply chain. IEEE Trans. VLSI Syst. 28(4), 954–967 (2020)

    Article  Google Scholar 

  5. Prinetto, P., and Roascio, G.: Hardware security, vulnerabilities, and attacks: a comprehensive taxonomy. In ITASEC 177–189 (2020)

  6. De, P., Mandal, C., Prampalli, U.: Path-balanced logic design to realize block ciphers resistant to power and timing attacks. IEEE Trans. VLSI Syst. 27(5), 1080–1092 (2019)

    Article  Google Scholar 

  7. Wang, W., Standaert, Y.F.X., Liu, J., Guo, Z., Gu, D.: Ridge-based DPA: improvement of differential power analysis for nanoscale chips. IEEE Trans. Inform. Forensic Secur. 13(5), 1301–1316 (2018)

    Article  Google Scholar 

  8. Rossi, D., Tenentes, V., Yang, S., Khursheed, S., Al-Hashimi, B.M.: Aging benefits in nanometer CMOS designs. IEEE Trans. Circuits Syst. II Exp. Briefs 64(3), 324–328 (2017)

    Google Scholar 

  9. de Cnudde, T., Nikova, S.: Securing the present block cipher against combined side-channel analysis and fault attacks. IEEE Trans. Very Large Scale Integ. Syst. 25(12), 3291–3301 (2017)

    Article  Google Scholar 

  10. Shanmugham, S.R., Paramasivam, S.: Survey on power analysis attacks and its impact on intelligent sensor networks. IET Wireless Sensor Syst. 8(6), 295–304 (2018)

    Article  Google Scholar 

  11. Tena-Sanchez, E., Castro, J., Acosta, A.J.: A methodology for optimized design of secure differential logic gates for DPA resistant circuits. IEEE J. Emerg. Select Topics Circuits Syst. 4(2), 203–215 (2014)

    Article  Google Scholar 

  12. Kumar, S.D., Thapliyal, H., Mohammad, A.: FinSAL: a novel FinFET based secure adiabatic logic for energy-efficient and DPA resistant IoT devices. IEEE Trans. Comput Aided Design Integr. Circuits Syst. 37(1), 110 (2017)

    Article  Google Scholar 

  13. Avital, M., Dagan, H., Keren, O., Fish, A.: Randomized multitopology logic against differential power analysis. IEEE Trans. VLSI Syst. 23(4), 702–711 (2015)

    Article  Google Scholar 

  14. Tanimura, K., Dutt, N.D.: HDRL: homogeneous dual-rail logic for DPA attack resistive secure circuit design. IEEE Embed. Syst. Lett. 4(3), 57–60 (2012)

    Article  Google Scholar 

  15. Kumar, S.D., Thapliyal, H., Mohammad, A.: EE-SPFAL: a novel energy-efficient secure positive feedback adiabatic logic for DPA resistant RFID and smart card. IEEE Trans. Emerg. Topics Comput. 7(2), 281–293 (2019)

    Article  Google Scholar 

  16. Saini, H., Gupta, A.: Constant power consumption design of novel differential logic gate for immunity against differential power analysis. IET Circuits Devices Syst. 13(1), 103–109 (2018)

    Article  Google Scholar 

  17. Bellizia, D., Bongiovanni, S., Monsurro, P., Scotti, G., Trifiletti, A.: Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications. IEEE Trans. Emerg. Topics Comput. 5(3), 329–339 (2017)

    Article  Google Scholar 

  18. Delgado-Lozano, I. M., Tena-Sanchez, E., Nunez J., and Acosta, A. J.: Design and analysis of secure emerging crypto-hardware using HyperFET devices IEEE Trans. Emerg. Topics in Comput. 9(2), 787–796 (2020)

  19. Hanyu, T., Endoh, T., Suzuki, D., Koike, H., Ma, Y., Onizawa, N., Natsui, M., Ikeda, S., Ohno, H.: Standby-power-free integrated circuits using MTJ-based VLSI computing. Proc. IEEE. 104(10), 1844–1863 (2016)

    Article  Google Scholar 

  20. Zhu, L., Bamberg, L., Agnesina, A., Catthoor, F., Milojevic, D., Komalan, M., Ryckaert, J., Garcia-Ortiz, A., Lim, S.K.: Heterogeneous 3D integration for a RISC-V system with STT-MRAM. IEEE Computer Arch. Lett. 19(1), 51–54 (2020)

    Article  Google Scholar 

  21. Shi, Y., Oh, S., Huang, Z., Lu, X., Kang, S.H. and Kuzum, D.: Performance prospects of deeply scaled spin-transfer torque magnetic random-access memory for in-memory computing IEEE Electron Device Lett. (2020)

  22. Deng, E., Zhang, Y., Klein, J.O., Ravelsona, D., Chappert, C., Zhao, W.: Low power magnetic full-adder based on spin transfer torque MRAM. IEEE Trans. Magnet. 49(9), 4982–4987 (2013)

    Article  Google Scholar 

  23. Deng, E., Zhang, Y., Kang, W., Dieny, B., Klein, J.O., Prenat, G., Zhao, W.: Synchronous 8-bit non-volatile full-adder based on spin transfer torque magnetic tunnel junction. IEEE Trans. Circuits Syst. I Regul. Pap. 62(7), 1757–1765 (2015)

    Article  Google Scholar 

  24. Cai, H., Wang, Y., Naviner, L.A., Zhao, W.: Robust ultra-low power non-volatile logic-in-memory circuits in FD-SOI technology. IEEE Trans Circuits Syst. I Regular Papers. 64(4), 847–857 (2016)

    Article  Google Scholar 

  25. Kumbhare, V.R., Kumar, R., Majumder, M.K., Kumar, S., Paltani, P.P., Kaushik, B.K., Sharma, R.: High-speed interconnects: history, evolution, and the road ahead. IEEE Microwave Mag. 23(8), 66–82 (2022)

    Article  Google Scholar 

  26. Kumar, S.D., Thapliyal, H.: Exploration of non-volatile MTJ/CMOS circuits for DPA-resistant embedded hardware. IEEE Trans. Magnet. 55(12), 1–8 (2019)

    Article  Google Scholar 

  27. Resta, G.V., Leonhardt, A., Balaji, Y.: Devices and circuits using novel 2-D materials: a perspective for future VLSI systems. IEEE Trans. VLSI Syst. 27(7), 1486–1503 (2019)

    Article  Google Scholar 

  28. Gopireddy, B., Skarlatos, D., Zhu, W., and Torrellas, J.: HetCore: TFET-CMOS hetero-device architecture for CPUs and GPUs. ACM/IEEE 45th Annual International Symposium on Computer Architecture. 802–815(2018)

  29. Kino, H., Fukushima, T., Tanaka, T.: Generation of STDP With non-volatile tunnel-FET memory for large-scale and low-power spiking neural networks. IEEE J. Electron Dev. Soc. 8, 1266–1271 (2020)

    Article  Google Scholar 

  30. Aditya, J., Vallabhaneni, H., Vaddi, R.: Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. IET Circuits Devices Syst. 10(6), 522–527 (2016)

    Article  Google Scholar 

  31. Lin Z., et al.: Challenges and solutions of the TFET circuit design IEEE Trans Circuits Syst. I: Regular Papers. 67(12), 4918–4931(2020)

  32. Aditya, J., et al.: Tunneling field effect transistors for enhancing energy efficiency and hardware security of IoT platforms: challenges and opportunities. In Proc. IEEE Int. Symp. Circuits and Systems (ISCAS). 1–5(2018)

  33. Bi, Y., et al.: Tunnel FET current mode logic for DPA-resilient circuit designs. IEEE Trans. Emerg. Top. Comput. 5(3), 340–352 (2017)

    Article  Google Scholar 

  34. Thapliyal, H., Varun, T. S. S., and Dinesh Kumar, S.: Low-power and secure lightweight cryptography via TFET-based energy recovery circuits In Proc IEEE Int Conf. Rebooting Comput., Washington. 1–4(2017)

  35. Chen, A., et al.: Using emerging technologies for hardware security beyond PUFs. In IEEE Design, Automation & Test Conf. & Exhibition, Dresden. 1544–1549(2016)

  36. Aditya, J., Majumder, M.K., Sahoo, S.K., Vaddi, R.: Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks. IET Circuits Devices Syst. 13(5), 689–695 (2019)

    Article  Google Scholar 

  37. Aditya, J., Majumder, M.K., Sahoo, S.K., Vaddi, R.: Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator. IET Circuits Devices Syst. 14(5), 640–647 (2020)

    Article  Google Scholar 

  38. Aditya, J., Majumder, M.K., Sahoo, S.K., Vaddi, R.: Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage. Int. J. Circuit Theory Appl. 48(4), 524–538 (2020)

    Article  Google Scholar 

  39. Liu, H., Narayanan, V., Datta, S, et al.: III-V Tunnel FET model. version 1.0.1. 2015. https://nanohub.org/publications/12/2

  40. Zhang, Y., et al.: Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions. IEEE Trans. Electron Devices. 59(3), 819–826 (2012)

    Article  Google Scholar 

  41. Hansen, M.C., Yalcin, H., Hayes, J.P.: Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering. IEEE Design Test Comput. 16(3), 72–80 (1999)

    Article  Google Scholar 

Download references

Funding

The authors have not disclosed any funding.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Hyderabad, 500075, India

    Aditya Japa

  2. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Hyderabad, 500078, India

    Subhendu K. Sahoo

  3. Department of Electronics and Communication, School of Engineering and Applied Sciences, SRM University, Amaravati, A.P, 522502, India

    Ramesh Vaddi

  4. Department of Electronics and Communication Engineering, International Institute of Information Technology, Naya Raipur, 493661, India

    Manoj Kumar Majumder

Authors
  1. Aditya Japa
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Subhendu K. Sahoo
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ramesh Vaddi
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Manoj Kumar Majumder
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Aditya Japa.

Ethics declarations

Conflict of interest

The authors have not disclosed any competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Japa, A., Sahoo, S.K., Vaddi, R. et al. Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption. J Comput Electron 22, 178–189 (2023). https://doi.org/10.1007/s10825-022-01958-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-022-01958-x

Keywords

Search

Navigation