Skip to main content
SpringerLink
Log in

Temperature-dependent short-channel parameters of FinFETs

  • Published:
Journal of Computational Electronics Aims and scope Submit manuscript

Abstract

The remarkable development and continual proliferation of research in the nanotechnology field have led to improvement in the efficiency of elementary devices. To improve their performance, the parameters of such devices can be scaled down while optimizing their characteristics. However, this simultaneously results in degraded switching characteristics and the appearance of short-channel effects. Multigate-based fin-shaped field-effect transistors (FinFETs) represent a new option to address all these problems. However, thermal failure of FinFET devices under nominal operating conditions is an important issue in the design and implementation of high-speed semiconductor devices. It is also seen that bulk FinFETs exhibit better thermal performance compared with silicon-on-insulator FinFETs. In the work presented herein, various FinFET characteristics including the subthreshold swing, drain-induced barrier lowering, threshold voltage, and drain current were investigated as functions of temperature. The (effective) channel length is larger than the physical gate length (in off-state) due to the undoped underlap regions. This paper also discusses the effects of drain, source, and gate overlap.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Revathy, G., Rajak, A.: A survey on FinFETs: technology, pros, cons and improvement prospects. Int. J. Adv. Technol. Eng. Sci. 2(10), 2014

  2. Chen, M.C., Lin, C.H., Hou, Y.F., Chen, Y.J., Lin, C.Y., Hsueh, F.K., Liu, H.L., Liu, C.T., Wang, B.W., Chen, H.C., Chen, C.C., Chen, S.H., Wu, C.T., Lai, T.Y., Lee, M.Y., Wu, B.W., Wu, C.S., Yang, I., Hsieh, Y.P., Ho, C., Wang, T., Sachid, A.B., Hu, C., Yang, F.L.: A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin. In: IEEE VLSI Technology (VLSIT), 2013 Symposium on (2013)

  3. Chen, M.C., Li, K.S., Li, L.J., Lu, A.Y., Li, M.Y., Chang, Y.H., Lin, C.H., Chen, Y.J., Hou, Y.F., Chen, C.C. and Wu, B.W., Wu, C.S., Yang, I., Lee, Y.J., Shieh, J.M., Yeh, W.K., Shih, J.H., Su, P.C., Sachid, A.B., Wang, T., Yang, F.L., Hu, C.: TMD FinFET with 4 nm thin body and back gate control for future low power technology. In: Electron Devices Meeting (IEDM), 2015 IEEE International. IEEE, (2015)

  4. Wang, M.C.: Independent-Gate FinFET circuit design methodology. IAENG Int. J. Comput. Sci. 37(1), 1–8

    MathSciNet  Google Scholar 

  5. Maity, S., Bhunia, C.T., Sahu, P.P.: Improvement in optical and structural properties of ZnO thin film through hexagonal nanopillar formation to improve the efficiency of Si-ZnO heterojunction solar cell. J. Phys. D Appl. Phys. (2016). https://doi.org/10.1088/0022-3727/49/20/205106

    Google Scholar 

  6. Maity, S., Muchahary, D., Sahu, P.: Enhancing responsivity and detectevity of Si-ZnO photo detector with growth of densely packed and aligned hexagonal nano-rods. IEEE Trans. Nanotechnol. (2017). https://doi.org/10.1109/TNANO.2017.2726101

    Google Scholar 

  7. Maity, S., Metya, S.K., Bhunia, C.K., Chakraborty, P., Sahu, P.P.: Improvement of front side contact and quantum efficiency of c-Si solar cell through light induced plating. Opt. Quantum Electron. 47(10), 3391–3404 (2015). https://doi.org/10.1007/s11082-015-0215-1

    Article  Google Scholar 

  8. Hasan, N., Maity, S., Sarkar, A., Bhunia, C.T., Acharjee, D., Joseph, A.M.: Simulation and fabrication of SAW based gas sensor through modification of surface state of active layer and electrode orientation for enhanced H2 gas sensing. J. Electron. Mater. IEEE (TMS) (2016). https://doi.org/10.1007/s11664-016-5128-7

    Google Scholar 

  9. Jha, N.K., Chen, D.: Nanoelectronic Circuit Design. Springer, Berlin (2011)

    Book  Google Scholar 

  10. Min, K.I.M.A., Oni, B.H.H.S.: Review on: major barriers of FinFET scaling. Int. J. VLSI Des. Commun. Syst. 3(2), 208–211 (2015)

    Google Scholar 

  11. Veshala, M., Jatooth, R., Reddy, K.R.: Reduction of short-channel effects in FinFET. Int. J. Eng. Innov. Technol. (IJEIT) 2(9), 118–124 (2013)

    Google Scholar 

  12. Baedi, J., Maleki, A., Noorodin, S.: Comparing the performance of FinFET SoI and FinFET bulk. Scinzer J. Eng. 2(3), 21–27 (2016)

    Google Scholar 

  13. Hadia, S.K., Patel, R.R., Kosta, Y.P.: FinFET architecture analysis and fabrication mechanism. J. Comput. Sci. 8(5), 235–240 (2011)

    Google Scholar 

  14. Sathe, M.S., Sarwade, N.P.: Power optimization at nanoscale using FinFETs and its comparison with CMOS. Int. J. Comput. Eng. Appl. 6, 33–41 (2014)

    Google Scholar 

  15. Lee, J.-H.: Highly scalable saddle MOSFET for high density and high performance DRAM. IEEE Electron. Device. Lett. 26(9), 690–692 (2005)

    Article  Google Scholar 

  16. Lawrence, B., Rubia, J.: Review of Fin FET technology and circuit design challenges. J. Eng. Res. Appl. 5(121), 2248–962277 (2015)

    Google Scholar 

  17. Bhattacharya, D., Jha, N.K.: FinFETs: from devices to architectures. Adv. Electron. 2014, 1–21 (2014)

    Article  Google Scholar 

  18. Arasteh, A., Moaiyeri, M.H., Taheri, M.R., Navi, K., Bagherzadeh, N.: An energy and area efficient 4:2 compressor based on FinFETs. Integr. VLSI J. 60, 224–231 (2018)

    Article  Google Scholar 

  19. Moaiyeri, M.H., Razi, F.: Performance analysis and enhancement of 10-nm GAA CNTFET-based circuits in the presence of CNT-metal contact resistance. J. Comput. Electron. 16(2), 240–252 (2017)

    Article  Google Scholar 

  20. Sayyah Ensan, S., Moaiyeri, M.H., Hessabi, S.: A robust and low-power near-threshold SRAM in 10-nm FinFET technology. Analog Integr. Circ. Sig. Process. 94(3), 497–506 (2018)

    Article  Google Scholar 

  21. Nesamani, I.F.P., Divakaran, R.P., Prabha, V.L., Sujith, M.B.: Source drain engineering in FinFET—a review. Int. J. Eng. Trends Technol. (IJETT) 8(9), 472–475 (2014)

    Article  Google Scholar 

  22. Das, R.R., Maity, S., Muchahary, D., Bhunia, C.T.: Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material. Superlattices Microstruct. 103, 262–269 (2017)

    Article  Google Scholar 

  23. Yu, B., Chang, L., Ahmed, S., Wang, H., Bell, S., Yang, C.Y., Tabery, C., Ho, C., Xiang, Q., King, T.J., Bokor, J., Hu, C., Lin, M.R., Kyser, D.: Fin-FET scaling to 10 nm gate length. In: International Electron Devices Meeting (IEDM) Technical Digest, IEEE, pp. 251–254 (2002)

  24. Sylvester, D., Hu, C.: Analytical modeling and characterization of deep submicron interconnects. Proc. IEEE 89(5), 698–704 (2001)

    Article  Google Scholar 

  25. Woo, D.S., Lee, J.H., Choi, W.Y., Choi, B.Y., Choi, Y.J., Lee, J.D., Park, B.G.: Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile. IEEE Trans. Nanotechnol. 1(4), 233–236 (2002)

    Article  Google Scholar 

  26. El, N., Boukortt, I., Informatiche, M.E., Patanè, S., Informatiche, M.E.: Effects of High-k dielectric materials on electrical characteristics of DG n-FinFETs. Int. J. Comput. Appl. 139(10), 28–32 (2016)

    Google Scholar 

  27. Saini, G., Rana, A.K.: Physical scaling limits of FinFET structure: a simulation study. Int. J. VLSI Des. Commun. Syst. 2(1), 26–35 (2011)

    Article  Google Scholar 

  28. Van Zeghbroeck, B.: Principles of Semiconductor Devices. Prentice Hall PTR (2007)

  29. Poiroux, T., Vinet, M., Faynot, O., Widiez, J., Lolivier, J., Ernst, T., Previtali, B., Deleonibus, S.: Multiple gate devices: advantages and challenges. Microelectron. Eng. 80, 378 (2005)

    Article  Google Scholar 

  30. Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., Hoffmann, T., Johnson, K., Kenyon, C., Klaus, J., McIntyre, B., Mistry, K., Murthy, A., Sandford, J., Silberstein, M., Sivakumar, S., Smith, P., Zawadzki, K., Thompson, S., Bohr, M.: A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: IEDM Technical Digest, pp. 978–980, 2003

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology, Agartala, 799046, India

    Rinku Rani Das, Atanu Choudhury & Apurba Chakraborty

  2. Department of Electronics and Communication Engineering, Tezpur University, Napaam, Tezpur, Sonitpur, Assam, 784028, India

    Santanu Maity & Partha P. Sahu

  3. Durgapur Institute of Advanced Technology and Management, Jawaharlal, Nehru Ave, Durgapur, West Bengal, 713214, India

    C. T. Bhunia

Authors
  1. Rinku Rani Das
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Santanu Maity
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Atanu Choudhury
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Apurba Chakraborty
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. C. T. Bhunia
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Partha P. Sahu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Santanu Maity.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Das, R.R., Maity, S., Choudhury, A. et al. Temperature-dependent short-channel parameters of FinFETs. J Comput Electron 17, 1001–1012 (2018). https://doi.org/10.1007/s10825-018-1212-y

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10825-018-1212-y

Keywords

Search

Navigation