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Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation

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Abstract

In this paper, silicon nanotube field effect transistors (SiNT-FETs) are investigated for independent gate operation using 3D numerical simulation. The parameters, \(\mathrm{I_{ON} , I_{OFF}, V_{T}}\), and the unity gain cut-off frequency \(\mathrm{(f_{T}}\)) are studied in the independent-gate mode. The SiNT-FET we have considered has two gates, namely outer and inner gates, and can be simultaneously driven or independently driven. The physical gate oxide thicknesses of the outer and inner gates of the device are to be converted into effective gate oxide thicknesses due to the non-Euclidean geometry associated with the tube structure. The effective gate oxide thicknesses are different for the same outer and inner physical gate oxide thickness. Since the inner and outer gates are asymmetric, the device parameters extracted at the outer and inner gates are different. Since the independent gate operation allows dynamic threshold voltage adjustment, a model to predict the threshold voltage also known as the threshold voltage sensitivity model is developed for the SiNT device by modifying the double gate FinFET model. These models are verified by TCAD simulation results to validate their accuracy.

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References

  1. Kim, K., Fossum, J.G.: Double-gate CMOS: symmetrical—versus asymmetrical-gate devices. IEEE Trans. Electron Devices 48(2), 294–299 (2001)

    Article  Google Scholar 

  2. Lim, H., Fossum, J.G.: Threshold voltage of thin-film silicon-on-insulator MOSFETs. IEEE Trans. Electron Devices 30, 1244–1251 (1983)

    Article  Google Scholar 

  3. Liu, Y.X. et al.: Flexible threshold voltage FinFETs with independent double gates and an ideal rectangular cross section Si-Fin channel. In: IEDM Tech Dig., pp. 986–988 (2003)

  4. Mathew, L., Du, Y., Thean, A. V.-Y., Sadd, M., Vandooren, A., Prher, C., Steehehens, T., Mm, R., Rar, R., Zavala, M., Sing, D., Kafwl, S., Hughes, J., Shimer, R., Jaflepalfi, S., Wmmen, F., Zhangz, W., Nguyen, Y.: CMOS vertical multiple independent gate field effect transistor (MIGFET). In: IEEE International SOI Conference (2004)

  5. Zhang, W., Fossum, J.G., Mathew, L., Du, Y.: Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans. Electron Devices 52(10), 2198–2206 (2005)

    Article  Google Scholar 

  6. Shrivastava, M., Baghini, M.S., Sachid, A.B., Sharma, D.K., Rao, V.R.: A novel and robust approach for common mode feedback using IDDG FinFET. IEEE Trans. Electron Devices 55(11), 3274–3282 (2008)

    Article  Google Scholar 

  7. Nagarajan, K.K., Srinivasan, R.: Investigation of tunable characteristics of independently driven double gate FinFETs in analog/RF domain using TCAD simulations. J. Comput. Theor. Nanosci. 11, 821–826 (2014)

    Article  Google Scholar 

  8. Tekleab, D., Tran, H.H., Slight, J.W., Jeffrey, S.W., Dureseti, C.: Silicon nanotube MOSFET. U.S. Patent 0,217,468 (2012)

  9. Tekleab, D.: Device performance of silicon nanotube field effect transistor. IEEE Electron Device Lett. 35(5), 506–508 (2014)

    Article  Google Scholar 

  10. Fahad, H.M., Hussain, M.M.: High-performance silicon nanotube tunneling FET for ultralow-power logic applications. IEEE Trans. on Electron Devices 60(3), 1034–1039 (2003)

    Article  Google Scholar 

  11. Ambika, R., Srinivasan, R.: Performnace analysis of n-type junctionless silicon nanotube field effect transistor. J. Nanoelectron. Optoelectron. 11, 1–7 (2016)

    Article  Google Scholar 

  12. Synopsys Sentaurus Device User Guide Version-A (2008–2009)

  13. Colinge, J.-P.: Finfets and Other Multigate Transistors. Springer, Berlin (2007)

  14. Auth, C.P., Plummer, J.D.: Scaling Theory for cylindrical fully-depleted, surrounding-gate MOSFET’s. IEEE Electron Device Lett. 18(2), 74–76 (1997)

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Information Technology, SSN College of engineering, Kalavakkam, Chennai, Tamilnadu, India

    R. Ambika & R. Srinivasan

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  1. R. Ambika
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  2. R. Srinivasan
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Ambika, R., Srinivasan, R. Analysis of independent gate operation in Si nano tube FET and threshold prediction model using 3D numerical simulation. J Comput Electron 15, 778–786 (2016). https://doi.org/10.1007/s10825-016-0822-5

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  • DOI: https://doi.org/10.1007/s10825-016-0822-5

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