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Designing of Parity Preserving Reversible Vedic Multiplier

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Abstract

Reversible logic is used in designing low-power CMOS circuits, optical information processing, and quantum computing. Moreover, using parity preserving gates in reversible circuits provides additional reliability in error detection. In this paper, a new parity preserving reversible block is presented. Also a 2 × 2 parity preserving reversible Vedic multiplier circuit is proposed. Then a 4 × 4 parity preserving reversible Vedic multiplier is presented. Afterward, a reversible Vedic multiplier in n × n dimensions is presented. In fact, a circuit in various dimensions is presented in this section. Finally, a computational relation for the proposed circuit is obtained to calculate the quantum cost of the circuit in desired dimensions. The proposed reversible multiplier circuits are evaluated in 2 × 2 and 4 × 4 dimensions compared to existing reversible logic-based multiplier circuits. The quantum costs, the number of constant inputs and the number of garbage outputs are significantly decreased in the suggested reversible multiplier circuits.

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Authors and Affiliations

  1. Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran

    Meysam Rashno & Mohammad Mosleh

  2. Department of Computer Engineering, Yadegar -e- Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

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  1. Meysam Rashno
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  2. Majid Haghparast
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  3. Mohammad Mosleh
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Correspondence to Majid Haghparast.

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Rashno, M., Haghparast, M. & Mosleh, M. Designing of Parity Preserving Reversible Vedic Multiplier. Int J Theor Phys 60, 3024–3040 (2021). https://doi.org/10.1007/s10773-021-04903-z

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  • DOI: https://doi.org/10.1007/s10773-021-04903-z

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