Abstract
Today, although intellectual properties (IP) and their reuse are common, their use is causing design security issues: illegal copying, counterfeiting, and reverse engineering. IP watermarking is an efficient way to detect an unauthorized IP copy or a counterfeit. In this context, many interesting solutions have been proposed. However, few combine the watermarking process with synthesis. This article presents a new solution, i.e. automatic low cost IP watermarking included in the high-level synthesis process. The proposed method differs from those cited in the literature as the marking is not material, but is based on mathematical relationships between numeric values as inputs and outputs at specified times. Some implementation results with Xilinx Virtex-5 FPGA that the proposed solution required a lower area and timing overhead than existing solutions.
Similar content being viewed by others
References
Pecht M, Tiku S (2006) Bogus! Electronic manufacturing and consumers confront a rising tide of counterfeit electronics. IEEE Spectr 43(5):37–46. Available from: http://www.spectrum.ieee.org/print/3423
http://www.agmaglobal.org (2012)
Gajski D et al. (1992) High-level synthesis: introduction to chip and system design. Kluwer Academic, Dordrecht
Coussy P, Morawiec A (eds) (2008) High-level synthesis from algorithm to digital circuit. Springer, Berlin. ISBN: 978-1-4020-8587-1
Aditya S, Kathai V (2008) Algorithmic synthesis using PICO, high-level synthesis from algorithm to digital circuit. In: High-level synthesis from algorithm to digital circuit, vol XVI, pp 53–74
Meredith M (2008) High-level SystemC synthesis with forte’s cynthesizer. In: High-level synthesis from algorithm to digital circuit, vol XVI, pp 75–97
Gupta S, Dutt N, Gupta R, Nicolau A (2003) Spark: a high-level synthesis framework for applying parallelizing compiler transformations. In: International conference on VLSI design, pp 461–466
Le Gal B, Casseau E (2009) Automated multimode system design for high performance DSP applications. In: Proceedings of the 17th EURASIP European conference on signal processing (EUSIPCO), Glasgow, Scotland, pp 1289–1293
Coussy P et al. (2008) GAUT—a high-level synthesis tool for DSP applications. In: High-level synthesis from algorithm to digital circuit, vol XVI. Springer, Berlin, pp 147–169
Abdel-Hamid T, Tahar S, Aboulhamid EM (2004) A survey on ip watermarking techniques. Des Autom Embed Syst 9(3):211–227
Wolfe G, Wong JL, Potkonjak M (2002) Watermarking graph partitioning solutions. IEEE Trans Comput-Aided Des Integr Circuits Syst 21(10):1196–1204
Kirovski D, Potkonjak M (2003) Local watermarks: methodology and application to behavioral synthesis. IEEE Trans Comput-Aided Des Integr Circuits Syst 22(9):1277–1283
Intellectual Property Protection Development Working Group (2001) Intellectual property protection: schemes, alternatives and discussion (white paper). Virtual Socket Interface Alliance
Chapman R, Durrani T (2000) IP Protection of DSP algorithms for system on chip implementation. IEEE Trans Signal Process 48(3):854–861
Rashid A, Asher J, Mangione-Smith W, Potkonjak M (1999) Hierarchical watermarking for protection of dsp filter cores. In: Proceedings of the IEEE custom integrated circuits conference, pp 39–42
Torunoglu I, Charbon E (2000) Watermarking-based copyright protection of sequential functions. IEEE J Solid-State Circuits 35(3):434–440
Oliveira AL (2001) Techniques for the creation of digital watermarks in sequential circuits designs. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(9):1101–1117
Kirovski D, Hwang YY, Potkonjak M, Cong J (1998) Intellectual property protection by watermarking combinational logic synthesis solutions. In: Proceedings of the IEEE/ACM international conference on computer-aided design (ICCAD), vol 98, pp 194–198
Koushanfar F, Hong I, Potkonjak M (2005) Behavioral synthesis techniques for intellectual property protection. ACM Trans Des Autom Electron Syst 10(3):523–545
Lach J, Mangione-Smith WH, Potkonjak M (1999) Robust FPGA intellectual property protection through multiple small watermarks. In: Proceedings of the 36th annual ACM/IEEE design automation conference (DAC’99). ACM Press, New York, pp 831–836
Jain A, Yuan L, Pari P, Qu G (2003) Zero overhead watermarking technique for FPGA designs. In: Proceedings of the 13th ACM Great Lakes symposium on VLSI (GLS-VLSI), pp 147–152
Sun G, Gao Z, Xu Y (2006) A watermarking system for ip protection by buffer insertion technique. In: Proceedings of the 7th international symposium on quality electronic design (ISQED’06). IEEE Computer Society, Washington, pp 671–675
Fan YC, Tsao HW (2003) Watermarking for intellectual property protection. Electron Lett 39(18):1316–1318
Arvind R, Nikhil S, Rosenband DL, Dave N (2004) High-level synthesis: an essential ingredient for designing complex ASICs. In: Proceedings of the IEEE/ACM international conference on computer-aided design (ICCAD’04), DC, USA, pp 775–782
Le Gal B, Andriamisaina C, Casseau E (2006) Bit-width aware high-level synthesis for digital signal processing systems. In: Proceeding of IEEE system-on-chip conference (SoC), Austin, Texas, pp 175–178
Sllame M, Drabek V (2002) An efficient list-based scheduling algorithm for high-level synthesis. In: Proceedings of the Euromicro symposium on digital systems design (DSD’02). IEEE Computer Society, Washington, p 316
Lim P, Kim T (2006) Thermal-aware high-level synthesis based on network flow method. In: Proceedings of the 4th international conference on Hardware/software codesign and system synthesis (CODES+ISSS’06). ACM Press, New York, pp 124–129
Ciesielski M, Askar S, Gomez-Prado D, Guillot J, Boutillon E (2007) Data-flow transformations using Taylor expansion diagrams. In: Proceedings of the conference on design, automation and test in Europe (DATE’07). EDA Consortium, San Jose, CA, USA, pp 455–460
Casseau E, Khan S, Le Gal B, Aubry W (2007) Multimode architecture design. In: Proceeding of design and architectures for signal and image processing workshop (DASIP), Grenoble, France
Le Gal B, Casseau E, Huet S (2008) Dynamic memory access management for high-performance DSP applications using high-level synthesis. IEEE Trans Very Large Scale Integr (VLSI) Syst 16(11):454–1464
Bossuet L, Gogniat G, Burleson W (2006) Dynamically configurable security for SRAM FPGA bitstreams. Int J Embed Syst, 2(1/2):73–85
Petitcolas F (2000) Watermarking schemes evaluation. IEEE Signal Process Mag 17(5):58–64
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Le Gal, B., Bossuet, L. Automatic low-cost IP watermarking technique based on output mark insertions. Des Autom Embed Syst 16, 71–92 (2012). https://doi.org/10.1007/s10617-012-9085-y
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10617-012-9085-y