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Application of intermediate CMOS layer-based defected ground structure to design a dual-band on-chip antenna with improved gain

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Abstract

In this paper, a novel CPW-fed dual-band on-chip antenna (OCA) by introducing a crossed bowtie shaped defected ground structure (CB-DGS) in one of the intermediate layers of the CMOS layout is proposed. In general, a CPW fed OCA has its ground plane on the same plane containing the antenna. However, in this work, a DGS is introduced in one of the intermediate layer using through silicon vias to obtain dual band characteristics with improved gain performance of the antenna. A 10 dB operating band of 9 GHz (2.25–11.75 GHz) is achieved by employing meandered loop miniaturization technique on the antenna designed on top CMOS layer, wherein the introduction of DGS layer enforced a comparatively less stop band at the middle of the operating band and the resultant structure offered a dual-band resonance characteristic at 3.1 GHz and 10.4 GHz. Here, the intermediate DGS layer between the top-layered antenna and silicon wafer reduces the substrate loss by preventing the coupling of the electromagnetic radiation with the substrate and enhances the antenna gain significantly at both the resonance frequencies respectively by \(+\) 16.01 dB and \(+\) 12.7 dB. A prototype of the proposed antenna structure is fabricated and the obtained simulated result is validated through experimental measurement.

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Acknowledgements

This work is supported by Visvesvaraya Ph.D. scheme, Ministry of Electronics and Information Technology (MeitY), Govt. of India, Grant No. PhD-MLA/4(29)/2015-16/01. Authors are thankful to Indian Nano User Program (INUP) run by MeitY at Indian Institute of Science, Bengaluru (IISc) for their lab support.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Amrita Vishwa Vidyapeetham, Coimbatore Campus, Coimbatore, Tamil Nadu, 641112, India

    Harshavardhan Singh

  2. Microwave and Antenna Research Laboratory (MARL), Department of Electronics and Communication Engineering, National Institute of Technology Durgapur, M.G. Road, Durgapur, West Bengal, 713209, India

    Sujit Kumar Mandal

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Singh, H., Mandal, S.K. Application of intermediate CMOS layer-based defected ground structure to design a dual-band on-chip antenna with improved gain. Analog Integr Circ Sig Process 118, 247–257 (2024). https://doi.org/10.1007/s10470-023-02212-5

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