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A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme

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Abstract

This paper describes a 10-bit digital-to-time converter (DTC) utilizing the glitch-free dual reset method and switchable supply regulation scheme for high linearity regardless of supply ripple noise and input signal speed. The proposed circuit is designed as a single-ended structure, and a delay control is configured as a thermometer code for high differential nonlinearity (DNL) with 32 × 32 array capacitors. The DTC is optimized with a 200 MHz input signal for utilizing wide bandwidth PLLs to decrease a conversion range and keep a high resolution of a time-to-digital converter to reduce the power dissipation and quantization noise, respectively. Besides, the high linearity is guaranteed in dynamic operation, which is the worst case of DTCs’ control. The output jitter is 159.3 fsrms at the maximal delay, while the DTC consumes 0.603 mW with a total area of 0.0085 mm2. The dynamic range is 429 ps with 433 fs resolution with 0.066-LSB DNL and 0.506-LSB integral nonlinearity, comparable to state-of-the-art.

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Acknowledgements

This work was supported by the National Research Foundation of Korea Grant funded by the Korean Government under Grant NRF-2019R1A2B5B01069415, and in part supported by Samsung Electronics.(Corresponding author: Minjae Lee.) The CAD tools were supported by IDEC, Daejeon, South Korea.

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Authors and Affiliations

  1. School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, A-407, 123 Cheomdan-Gwagiro, Buk-gu, Gwangju, KS008, Republic of Korea

    Inho Jung, Sunghyun Bae, Sinho Lee & Minjae Lee

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  1. Inho Jung
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  2. Sunghyun Bae
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  3. Sinho Lee
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  4. Minjae Lee
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Correspondence to Minjae Lee.

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Jung, I., Bae, S., Lee, S. et al. A 1 V 10-bit highly linear and monotonic digital-to-time converter with 0.066-LSB DNL utilizing a glitch-free dual reset method and switchable supply regulation scheme. Analog Integr Circ Sig Process 112, 185–196 (2022). https://doi.org/10.1007/s10470-022-02016-z

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  • DOI: https://doi.org/10.1007/s10470-022-02016-z

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