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A circuit-level inverter-based switched capacitor integrator model justified by post-layout simulations of an incremental sigma-delta converter

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Abstract

This paper proposes a circuit-level model of an inverter-based switched-capacitor (SC) integrator involved in a previously published incremental sigma-delta analog-to-digital converter (I\(\Sigma {\Delta }\) ADC) to explain the ADC resolution degradation observed in the post-layout simulation. A fine analysis of post-layout signals led to a new model of the integrator with parasitic capacitors. Then the model has been included in the I\(\Sigma {\Delta }\) ADC model, which has been simulated with Matlab. To get detailed results and be able to handle comparisons, various calibration techniques have been applied to the I\(\Sigma {\Delta }\) ADC outputs coming from post-layout simulation and from the new model so that a better resolution is achieved. The results show a good likeness of the error shapes and magnitudes for the new model compared to post-layout simulations. We deduce that the proposed model is a good representation of the degradation phenomena, this with a high level of confidence.

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Funding

Funding was provided by Université Paris-Saclay (FR); Sorbonne Université; Centralesupélec; CNRS; Laboratoire GEEPS.

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Authors and Affiliations

  1. CentraleSupèlec, CNRS, Laboratoire de Gènie Electrique et Electronique de Paris, Universitè Paris-Saclay, 91192, Gif-sur-Yvette, France

    Li Huang, Caroline Lelandais-Perrault, Anthony Kolar & Philippe Bénabès

  2. CNRS, Laboratoire de Gènie Electrique et Electronique de Paris, Sorbonne Universitè, 75252, Paris, France

    Li Huang, Caroline Lelandais-Perrault, Anthony Kolar & Philippe Bénabès

Authors
  1. Li Huang
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  2. Caroline Lelandais-Perrault
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  3. Anthony Kolar
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  4. Philippe Bénabès
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Correspondence to Li Huang.

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Huang, L., Lelandais-Perrault, C., Kolar, A. et al. A circuit-level inverter-based switched capacitor integrator model justified by post-layout simulations of an incremental sigma-delta converter. Analog Integr Circ Sig Process 107, 51–64 (2021). https://doi.org/10.1007/s10470-021-01813-2

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