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A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor

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Abstract

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting as well as offset calibrating function. A 1.5-Mpixel 60-fps CIS with the ASP is fabricated in a 0.13 μm 1P4M CMOS mixed signal process. The experiment results indicate the sensor can normally capture images without missing code. Moreover, the measured maximum gain error of the PGA is 1.6%, and the power dissipation is 16.5 mW for single ASP.

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References

  1. Fossum, E. R. (1997). CMOS image sensors: Electronic camera on a chip. IEEE Transactions on Electron Devices, 44, 1689. https://doi.org/10.1109/16.628824.

    Article  Google Scholar 

  2. El-Desouki, M., et al. (2009). CMOS image sensors for high speed applications. Sensors. https://doi.org/10.3390/s90100430.

    Article  Google Scholar 

  3. Y. Chae et al. (2010). A 2.1 Mpixel 120 frame/s CMOS image sensor with column-parallel sigma-delta ADC architecture. In:IEEE ISSCC Dig.Tech. Papers 394. https://doi.org/10.1109/ISSCC.2010.5433974.

  4. Kim, Min-Kyu, et al. (2016). A fast multiple sampling method for low-noise CMOS image sensors with column-parallel 12-bit SAR ADCs. Sensors., 16, 27. https://doi.org/10.3390/s16010027.

    Article  Google Scholar 

  5. Sugo, H. et al. (2016). A Dead-time Free Global Shutter CMOS Image Sensor with in-pixel LOFIC and ADC using Pixel-wise Connections. In IEEE Symp. VLSI Circuits (pp 224–225). https://doi.org/10.1109/vlsic.2016.7573544.

  6. Sakakibara M. et al. (2018). A Back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC. In IEEE ISSCC Dig.Tech. Papers (pp 79–80). https://doi.org/10.1109/isscc.2018.8310193.

  7. http://www.imapsfrance.org/medical122/Y1%20-%20Endoscopy&X-Ray%20IS.pdf.

  8. Schlegel, S., et al. (2012). Endoscope with flexible Tip and Chip on-the Tip Camera. World Congress on Medical Physics and Biomedical Engineering. https://doi.org/10.1007/978-3-642-29305-4_554.

    Article  Google Scholar 

  9. Wang Z, et al. CMOS IC Design for Wireless Medical and Health Care, (Springer New York Heidelberg Dordrecht London, 2013)163, Chapter 6.

  10. Zhang M. et al. (2008). A low power CMOS image sensor design for wireless endoscopy capsule. In Proc. IEEE Biomedical Circuits and Systems Conference. (pp. 397–400). https://doi.org/10.1109/biocas.2008.4696958.

  11. Razavi, B. (2015). Design of Analog.CMOS integrated circuits (2nd ed., p. 564). New York: McGraw-Hill Education.

    Google Scholar 

  12. Lim, Y. et al. (2014). A 100 MS/s 10.5b 2.46 mW comparator-less pipeline ADC using self-biased ring amplifiers. In IEEE ISSCC Dig.Tech. Papers (pp. 202–203). https://doi.org/10.1109/jssc.2015.2453332.

  13. Flandre, D., et al. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. IEEE Journal of Solid-State Circuits. https://doi.org/10.1109/4.597291.

    Article  Google Scholar 

  14. Abo, A. M., & Gray, P. R. (1999). A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE Journal of Solid-State Circuits, 34, 599. https://doi.org/10.1109/jssc.1999.2453332.

    Article  Google Scholar 

  15. Abo, A. M. (1999). Design for Reliability of Low-voltage Switched-capacitor Circuits. Ph.D. Dissertation, University of California, Berkeley.

  16. Cho, T. B., & Gray, P. R. (1995). A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE Journal of Solid-State Circuits, 30, 166. https://doi.org/10.1109/4.364429.

    Article  Google Scholar 

  17. Shiraishi, K. et al. (2016). A 1.2e - Temporal Noise 3D-Stacked CMOS Image Sensor with Comparator-Based Multiple-Sampling PGA,” ISSCC Dig. Tech. Papers. (pp. 122–123). https://doi.org/10.1109/isscc.2016.7417937.

  18. Kim, J.-B., et al. (2015). A low-power CMOS image sensor with area-efficient 14-bit Two-Step SA ADCs using pseudomultiple sampling method. IEEE Transactions on Circuits and Systems II: Express Briefs, 62, 451. https://doi.org/10.1109/TCASII.2014.2387531.

    Article  Google Scholar 

  19. Lee, J., et al. (2015). High frame-rate VGA CMOS image sensor using non-memory capacitor two-step single-slope ADCs. Transactions on Circuits and Systems I: Regular Papers, 62, 2155. https://doi.org/10.1109/tcsi.2015.2451791.

    Article  MathSciNet  Google Scholar 

  20. Kobayashi, M., et al. (2018). A 1.8 e −rms temporal noise over 110 dB dynamic range 3.4 µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers SS-ADC and multiple-accumulation shutter. IEEE Journal of Solid-State Circuits, 53, 219. https://doi.org/10.1109/jssc.2017.2737143.

    Article  Google Scholar 

  21. Kawahito, S. (2018). Column-Parallel ADCs for CMOS Image Sensors and Their FoM-Based Evaluations, IEICE Transactions on Electronics, E101.C, 7, 444-456.

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Acknowledgements

This work is sponsored by National Key Research and Development Project (No. 2018YFB2002604), Key foreign cooperation projects of Chinese Academy of Sciences (No. 172511KYSB20180080), and Foundation of Guizhou Educational Committee for Youths (QJH KY Zi [2018]) No.317.

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Authors and Affiliations

  1. Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, 100029, China

    Ming Chen, Li Zhou, Chengbin Zhang, Kunyu Wang, Cen Gao, Wenjing Xu & Jie Chen

  2. ZunYi Normal University, Zunyi, 563006, China

    YangJun Yang

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  1. Ming Chen
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  2. Li Zhou
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  8. Jie Chen
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Correspondence to Ming Chen.

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Chen, M., Zhou, L., Yang, Y. et al. A 15.5x-gain 0.29-mm2 CMOS readout circuit for 1.5-Mpixel 60-fps CMOS image sensor. Analog Integr Circ Sig Process 108, 89–99 (2021). https://doi.org/10.1007/s10470-020-01778-8

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