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A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications

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Abstract

This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current \(I_{\mathrm{on}}\), while the off current \(I_{\mathrm{off}}\) remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher \(I_{\mathrm{on}}\) are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science Pilani, Hyderabad Campus, Hyderabad, 500078, India

    Sanjay Vidhyadharan, Ramakant Yadav, Hariprasad Simhadri & Surya Shankar Dan

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  1. Sanjay Vidhyadharan
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  2. Ramakant Yadav
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  3. Hariprasad Simhadri
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  4. Surya Shankar Dan
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Correspondence to Sanjay Vidhyadharan.

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Vidhyadharan, S., Yadav, R., Simhadri, H. et al. A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications. Analog Integr Circ Sig Process 101, 109–117 (2019). https://doi.org/10.1007/s10470-019-01487-x

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  • DOI: https://doi.org/10.1007/s10470-019-01487-x

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