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56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology

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Abstract

A novel single-ended SRAM is proposed in this study, where the built-in self-refleshing data retention path has been utilized to reduce the SRAM cell area. In order to reduce the power-delay product, an analytical solution to derive the optimal number of the 5T cells on the BLB is reported in this paper. The proposed SRAM is implement by TSMC 90 nm CMOS technology. According to the measurement results, the energy dissipation per write/read operation is found to be 0.479/0.091 fJ provided that the SRAM cells is supplied a 0.6 V VDD supply.

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Acknowledgements

This investigation is partially supported by Ministry of Science and Technology under Grant MOST 104-2622-E-006-040-CC2, MOST 105-2218-E-110-006, and MOST 105-2-E-110-058. The authors would like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service and EDA tool support. The authors also like to thank Mr. C.-H. Liao for his assistance in the physical measurement of the SRAM chips.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan

    Chua-Chin Wang, Deng-Shain Wang & Sih-Yu Chen

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  1. Chua-Chin Wang
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  2. Deng-Shain Wang
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  3. Sih-Yu Chen
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Correspondence to Chua-Chin Wang.

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Wang, CC., Wang, DS. & Chen, SY. 56.67 fJ/bit single-ended disturb-free 5T loadless 4 kb SRAM using 90 nm CMOS technology. Analog Integr Circ Sig Process 96, 435–443 (2018). https://doi.org/10.1007/s10470-018-1186-5

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  • DOI: https://doi.org/10.1007/s10470-018-1186-5

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