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Design of sampled analog wavelet processor architecture for cochlear implant application

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Abstract

This paper presents the design of sampled analog wavelet processor architecture for cochlear implant application using discrete Haar wavelet transform. Basic element of sampled analog wavelet processor architecture is operational amplifier based switched capacitor integrator circuit. This architecture distributes input signal frequencies into different predefined frequency band and based on cochlear sensitivity region for different frequencies by using arbitrary tree structure. The presented architecture is beneficial in terms of processing time of input signal, area and complexity by avoiding quantization and encoding process part of data converter circuits. Simulation results for this architecture is carried out with CMOS 90 nm technology.

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Authors and Affiliations

  1. VLSI Division, School of Electronics, VIT University, Vellore, India

    Piyush M. Chaniyara, Prabhat Kumar Srivastava, B. Suresha & A. Subhakumar Reddy

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  1. Piyush M. Chaniyara
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  2. Prabhat Kumar Srivastava
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  3. B. Suresha
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  4. A. Subhakumar Reddy
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Correspondence to Piyush M. Chaniyara.

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Chaniyara, P.M., Srivastava, P.K., Suresha, B. et al. Design of sampled analog wavelet processor architecture for cochlear implant application. Analog Integr Circ Sig Process 86, 171–180 (2016). https://doi.org/10.1007/s10470-015-0642-8

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