Skip to main content
Log in

Delta–sigma DAC with jitter-shaper-reducing jitter noise

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

We present a novel delta–sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB and design and simulate the complete jitter shaper circuit in SPICE. We predict that the jitter shaper will improve the signal-to-noise ratio by 47.2 dB (MATLAB) up to 24.6 dB (SPICE).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22
Fig. 23
Fig. 24

Similar content being viewed by others

References

  1. Schreier, R., & Temes, G. C. (2004). An introduction to ΔΣ analog/digital converters (translated from the Japanese by T. Waho & A. Yasuda). Maruzen Co., Ltd.

  2. Cherry, J. A., & Snelgrove, W. M. (1999). Clock jitter and quantizer metastability in continuous-time delta–sigma modulators. IEEE Transactions on Circuits and Systems II, 46, 376–389.

    Article  Google Scholar 

  3. Fujimori, I., Nogi, A., & Sugimoto, T. (2000). A multibit delta–sigma audio DAC with 120-dB dynamic range. IEEE Journal of Solid-State Circuits, 35(8), 1066–1073.

    Article  Google Scholar 

  4. Kobayashi, H., Kurosawa, N., Miyauchi, I., Kawakami, S., Kogure, H., Komuro, T., & Sakayori, H. (2003). Timing error analysis in digital-to-analog converter—effects of sampling clock jitter and timing skew (Glitch). In 10th electronic devices and systems conference 2003, Brno, pp. 212–299.

Download references

Acknowledgments

This work was supported by the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Cadence Design Systems, Inc., San Jose, California, U.S.A.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Yuki Watanabe.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Watanabe, Y., Saikatsu, S., Yoshino, M. et al. Delta–sigma DAC with jitter-shaper-reducing jitter noise. Analog Integr Circ Sig Process 85, 243–251 (2015). https://doi.org/10.1007/s10470-015-0600-5

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-015-0600-5

Keywords

Navigation