Abstract
We present a novel delta–sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The jitter shaper is designed for a 0.18 µm CMOS and comprises switched capacitor and sample-and-hold circuits. We simulate the DSDAC in MATLAB and design and simulate the complete jitter shaper circuit in SPICE. We predict that the jitter shaper will improve the signal-to-noise ratio by 47.2 dB (MATLAB) up to 24.6 dB (SPICE).
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Acknowledgments
This work was supported by the VLSI Design and Education Center (VDEC), University of Tokyo, in collaboration with Cadence Design Systems, Inc., San Jose, California, U.S.A.
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Watanabe, Y., Saikatsu, S., Yoshino, M. et al. Delta–sigma DAC with jitter-shaper-reducing jitter noise. Analog Integr Circ Sig Process 85, 243–251 (2015). https://doi.org/10.1007/s10470-015-0600-5
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DOI: https://doi.org/10.1007/s10470-015-0600-5