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0.2–4.35 GHz highly linear CMOS balun-LNA with substrate noise optimization

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Abstract

A wideband CG–CS-based balun-LNA is proposed, with high linearity (IIP2 and IIP3) for multi-standard radio applications. By taking advantage of the common-gate transistor’s noise and distortion cancellation property in CG–CS-based balun topology, this balun-LNA just focuses on CS-stage’s noise and linearity improvement. Post-distortion technique with a p-MOSFET as auxiliary transistor is adopted to suppress the 2nd and 3rd nonlinear terms of the main transistor in CS-stage, and then across 0.2–4.35 GHz, above 34 dBm IIP2 and 7.5 dBm IIP3 with typical process corner is achieved. In addition, in order to reduce the considerable substrate noise from the main transistor in CS-stage, a large resistor is connected between its bulk and source terminal, which reduces the substrate noise contribution from 7.68 to 0.2 % and improves the noise figure (NF) at 1 GHz about 0.38 dB. This balun-LNA was designed in 0.18-μm CMOS, operates from 0.2 to 4.35 GHz, and dissipates 17.8 mW with 1.5-V supply. With typical process corner, this amplifier provides 17.2-dB maximum voltage gain and 2.5–3.2 dB NF.

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Acknowledgments

The authors would like to thank Information Science Laboratory Center of USTC for EDA tools support.

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Authors and Affiliations

  1. Department of Electronic Science and Technology, University of Science and Technology of China (USTC), Hefei, 230027, Anhui, People’s Republic of China

    Dong Huang, Weiqiang Qian, Mehdi Khan, Shengxi Diao & Fujiang Lin

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  1. Dong Huang
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  2. Weiqiang Qian
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  3. Mehdi Khan
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  4. Shengxi Diao
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  5. Fujiang Lin
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Correspondence to Fujiang Lin.

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Huang, D., Qian, W., Khan, M. et al. 0.2–4.35 GHz highly linear CMOS balun-LNA with substrate noise optimization. Analog Integr Circ Sig Process 83, 285–293 (2015). https://doi.org/10.1007/s10470-015-0533-z

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  • DOI: https://doi.org/10.1007/s10470-015-0533-z

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