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Analytical modeling of read noise margin of a CNFET based 6T SRAM cell

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Abstract

There is a pressing need to increase the levels of on-chip integration of SRAM, which offers serious design challenges in terms of power requirement and cell stability. Static noise margin is an important criterion to constitute SRAM stability. As the CMOS technology is facing numerous challenges due to feature size reductions, carbon nanotube field effect transistors (CNFET) has been recommended for high stability, high performance and low power SRAM cell design. In this paper the stability of CNFET based 6T SRAM cells is investigated analytically as well as by simulation. We have derived an explicit analytical expression for the read static noise margin as a function of device parameters. The SRAM is also simulated in HSPICE and the results are in good agreement with the result obtained from the analytic expression. Along with other parameters supply voltage is also considered as a variable in the analytic expression to observe its effect on the read static noise margin.

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Authors and Affiliations

  1. Techno India College of Technology, Kolkata, India

    Priyanka Saha

  2. Jadavpur University, Kolkata, India

    Amit Jain & Subir Kumar Sarkar

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  1. Priyanka Saha
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  2. Amit Jain
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  3. Subir Kumar Sarkar
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Correspondence to Priyanka Saha.

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Saha, P., Jain, A. & Sarkar, S.K. Analytical modeling of read noise margin of a CNFET based 6T SRAM cell. Analog Integr Circ Sig Process 83, 369–376 (2015). https://doi.org/10.1007/s10470-015-0523-1

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  • DOI: https://doi.org/10.1007/s10470-015-0523-1

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