Abstract
Driver circuits that save switching power by 25 % or more using LC resonance energy recovery are shown for use in clock and data networks. Resonant and other energy savings circuits are shown from global to local leaf cell clocking. A 10× operating frequency range with power reductions allows dynamic voltage and frequency scaling for power management. The resonance used only for the brief transition periods rather than the entire clock cycle and thus small on-chip inductors around 2 nH range are sufficient to support this timing. A new resonant driver that generates tracking pulses at each transition of clock for dual edge operation across scaled frequencies is proposed. The design is readily scaled from 90 to 45 nm in standard CMOS processes and beyond. It is robust with 50 % variation in component values for functionality and skew performance. The resulting power savings add up to 10’s of watts in high performance processors. Skew reductions are achieved without needing to increase the interconnect widths. A 40 % driver active area reduction is also achieved. The scheme is naturally compatible with dynamic logic allowing their increased use at lower power.
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Chan, S. C., Shepard, K. L., & Restle, P. J. (2005). Uniform-phase, uniform amplitude, resonant-load global clock distributions. IEEE Jounal of Solid-State Circuits, 40(1), 102–109.
Rosenfeld, J., & Friedman, E. (2007). Design methodology for global resonant H-tree clock distribution networks. IEEE Transactions on Very Large Scale Integration (VLSI) systems, 15(2), 135–148.
Xuchu, Hu, & Guthaus, M. R. (2011). Distributed LC resonant clock grid synthesis. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(2012), 2749–2760.
Chan, S. C., Restle, P. J., Bucelot, T. J., Liberty, J. S., Weitzel, S., Keaty, J. M., et al. (2009). A resonant global clock distribution for the cell broadband engine processor. IEEE Journal Of Solid-State Circuits, 44(1), 64–72.
Sathe, V. S., et al. (2013). Resonant-clock design for a power-efficient, high-volume x86–64 microprocessor. IEEE Journal Solid-state circuits, 48(1), 149–149.
Rabaey, J. M., Chandarakasan, A., & Nokolic, B. (2003). Digital integrated circuits: A design perspective. Mountain View: Prentice Hall.
Bezzam, I., Krishnan, S., & Raja, T. (2013). Low power low voltage wide frequency resonant clock and data circuits for SoC power reductions. Peru: IEEE Latin American Symposium on Circuits and Systems. 2013.
Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba (2011). Advanced Configuration and Power Interface (ACPI) is an open industry specification 5.0: http://www.acpi.info.
Sze, C.N., Restle, P., Nam, G.-J., Alpert, C.J.(2009). Clocking and the ISPD’09 clock synthesis contest. Proceedings of the ISPD, 2009, pp. 149–150.
Bezzam, I., Krishnan, S., and Mathiazhagan, C.(2012). Low power SoCs with resonant dynamic logic using inductors for energy recovery. VLSI and System-on-Chip (VLSI-SoC)
Terence, M.P., & James B.(2006). Null value propagation for FAST14 logic. US patent 7,053,664, May 2006.
Fuketa, H., Nomura, M., Takamiya, M., & Sakurai, T. (2013). Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37 V 980 kHz near-threshold logic circuits. IEEE Solid State Circuits Conference, 56, 436–437.
Campolo, D., Sitti, M., & Fearing, R. S. (2003). Efficient charge recovery method for driving piezoelectric actuators with quasi-square waves. IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, 50(1), 1–9.
Kim, C., & Kang, S. (2002). A low-swing clock double-edge triggered flip-flop. IEEE Journal Of Solid-State Circuits, 37(5), 648–652.
Mahmoodi, H., Tirumalashetty, V., Cooke, M., & Roy, K. (2009). Ultra low-power clocking scheme using energy recovery and clock gating. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 17(1), 33–44.
Esmaeili, S. E., Al-Khalili, A. J., & Cowan, G. E. R. (2012). Low-swing differential conditional capturing flip-flop for LC resonant clock distribution networks. IEEE Transactions On Very Large Scale Integration (VLSI) Systems, 20(8), 1547–1551.
Tschanz, J., Narendra, S., Chen, Z., Borkar, S., and Sachdev, M. (2001). Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. Proceedings of 2001 ISLPED, pp. 147–152, August 6-7, 2001, USA.
Drake, A. J., Nowka, K. J., Nguyen, T. Y., Burns, J. L., & Brown, R. B. (2004). Resonant clocking using distributed parasitic capacitance. IEEE Journal of Solid-State Circuits, 39(9), 1520–1528.
Guhaus, M. R., Wilke, G., & Reis, R. (2013). Revisiting automated physical synthesis of high-performance clock networks. ACM Transactions on Design Automation of Electronic Systems, 18(2), 31.
Rabaey, J. M. (2009). Low power design essentials. New York: Springer.
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The authors acknowledge valuable inputs from Dr. Mathew R. Guthaus of University of California Santa Cruz.
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Title of the journal: Springer Science & Business Media Analog Integrated Circuits and Signal Processing.
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Bezzam, I., Krishnan, S., Mathiazhagan, C. et al. Wide operating frequency resonant clock and data circuits for switching power reductions. Analog Integr Circ Sig Process 82, 113–124 (2015). https://doi.org/10.1007/s10470-014-0447-1
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DOI: https://doi.org/10.1007/s10470-014-0447-1