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Accuracy improvement of the output impedance model for capacitive down-converters

  • Mixed Signal Letter
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Abstract

Contemporary models fail to include the influence of the output buffer capacitor size on the performance of capacitive DC–DC converters. This letter examines the relevance of this dependency and shows how to adapt existing models in order to include it. The improved model is verified mathematically for down-converters, by means of Spice simulations and based on measurements of silicon integrated prototypes. Measurements demonstrate an accuracy improvement of up to 30 % compared with the conventional model.

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Authors and Affiliations

  1. Kasteelpark Arenberg 10, 3000, Leuven, Belgium

    Tom Van Breussegem & Michiel Steyaert

Authors
  1. Tom Van Breussegem
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  2. Michiel Steyaert
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Correspondence to Tom Van Breussegem.

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Van Breussegem, T., Steyaert, M. Accuracy improvement of the output impedance model for capacitive down-converters. Analog Integr Circ Sig Process 72, 271–277 (2012). https://doi.org/10.1007/s10470-012-9858-z

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  • DOI: https://doi.org/10.1007/s10470-012-9858-z

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