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Vernier parallel delay-line based time-to-digital converter

  • Mixed Signal Letter
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Abstract

This letter proposes a new parallel delay-line time-to-digital converter (TDC) architecture based on the Vernier principle. Two parallel delay-line stages with slightly different incremental step sizes are cascaded, resulting in a finer resolution compared to the traditional parallel delay line. A 2-bit TDC fabricated in a 0.18 μm CMOS technology demonstrates the principle with a time resolution of 2.5 ps and a differential nonlinearity of 0.13 LSB.

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Acknowledgment

The work described in this letter was supported by a grant from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project No. CUHK 416110).

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Authors and Affiliations

  1. Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, N. T., Hong Kong

    Chi-Tung Ko, Kong-Pang Pun & Andreas Gothenberg

Authors
  1. Chi-Tung Ko
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  2. Kong-Pang Pun
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  3. Andreas Gothenberg
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Correspondence to Kong-Pang Pun.

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Ko, CT., Pun, KP. & Gothenberg, A. Vernier parallel delay-line based time-to-digital converter. Analog Integr Circ Sig Process 71, 151–153 (2012). https://doi.org/10.1007/s10470-011-9766-7

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  • DOI: https://doi.org/10.1007/s10470-011-9766-7

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