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A CMOS broadband frequency synthesizer for DVB-C receiver

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Abstract

A 70∼900 MHz broadband PLL frequency synthesizer is developed for the single conversion DVB-C receiver in a standard 0.25 μm CMOS technology. The true 3-band VCO with a novel AAC (Auto-Amplitude Control) circuit provides a wideband amplitude stable output and a reliable startup without degrading the phase noise performance. A 16/17 dual-modulus prescaler with a new logic structure has increased the speed. The charge pump current is programmable for wide loop stabilization and phase noise optimization. The measured results show that the locked range of the frequency synthesizer is 70∼900 MHz. The worst phase noise at 1 k/10 k/100 k/1 MHz offset frequency is ordinal −65/−85/−112/−128 dBc/Hz and the spur at reference frequency is lower than −90 dBc.The frequency synthesizer chip dissipates only 16.2 mA from a 3.3 V supply.

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Acknowledgements

The authors would like to thank the co-workers from National ASIC System Engineering Technology Research Center of China, for the support of this work.

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  1. National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, 210096, China

    Jianhui Wu & Zuotian Chen

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  1. Jianhui Wu
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  2. Zuotian Chen
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Correspondence to Jianhui Wu.

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Wu, J., Chen, Z. A CMOS broadband frequency synthesizer for DVB-C receiver. Analog Integr Circ Sig Process 52, 109–115 (2007). https://doi.org/10.1007/s10470-007-9103-3

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  • DOI: https://doi.org/10.1007/s10470-007-9103-3

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