Abstract
In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimization variables are determined graphically. An enumeration algorithm implemented finds the global optimum layout that gives the highest quality factor in less than 1 s of CPU time with less function evaluations. The optimization method also gives the performance of all possible combinations that results the same inductance value. Subsequently important fundamental tradeoff of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is explored in few seconds. The method also gives other valuable information such as sensitivity of the inductance and quality factor to the layout design parameters. The accuracy of the proposed method is verified using a 3D electromagnetic simulator.
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This work was carried out using Intellisuite of IntelliSense Software Corp. procured under the NPSM project at Indian Institute of Technology Guwahati.
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Haobijam, G., Paily, R. Efficient optimization of integrated spiral inductor with bounding of layout design parameters. Analog Integr Circ Sig Process 51, 131–140 (2007). https://doi.org/10.1007/s10470-007-9061-9
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DOI: https://doi.org/10.1007/s10470-007-9061-9