Skip to main content
Log in

New layout strategies with improved matching performance

  • Regular Paper
  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, the systematic mismatch error in integrated circuits due to gradient effects is modeled and analyzed. Three layout strategies with improved matching performance are reviewed and summarized. The hexagonal tessellation pattern can cancel quadratic gradient errors with only 3 units for each device and has high area-efficiency when extended. Both the Nth-order circular symmetry patterns and Nth-order central symmetry patterns can cancel up to Nth-order gradient effects between two devices using 2N unit cells for each one. Among these three techniques, the central symmetry patterns have the best-reported matching performance for Manhattan structures; the circular-symmetry patterns have the best theoretical matching performance; and the hexagonal tessellation pattern has high density and high structural stability. The Nth-order central symmetry technique is compatible to all IC fabrication processes requiring no special design rules. Simulation results of these proposed techniques show better matching characteristics than other existing layout techniques under nonlinear gradient effects. Specifically, two pairs of P-poly resistors using 2nd and 3rd-order central symmetry patterns were fabricated and tested. Less than 0.04% mismatch and less than 0.002% mismatch were achieved for the 2nd and the 3rd-order structures, respectively.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. V. Gupta and G.A. Rincon-Mora, “Predicting the effects of error sources in bandgap reference circuits and evaluating their design implications.” Circuits Systems, 2002, MWSCAS-2002, vol. 3, pp. 575–578, Aug. 2002.

    Google Scholar 

  2. H.A. Alzaher and M. Ismail, “Robust low-distortion wideband CMOS current-follower.” Electronics Letters, vol. 35, no. 25, pp. 2203–2204, Dec. 1999.

    Article  Google Scholar 

  3. S. Lovett, M. Welten, A. Mathewson, and B. Mason, “Optimizing MOS transistor mismatch.” IEEE Journal of Solid-State Circuits, vol. 33, pp. 147–150, Jan. 1998.

    Article  Google Scholar 

  4. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching properties of MOS transistors.” IEEE Journal of Solid-State Circuits, vol. SC-24, pp 1433–1439, 1989.

    Article  Google Scholar 

  5. K. Lakshmikumar, R. Hadaway, and M. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design.” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057–1066, 1986.

    Article  Google Scholar 

  6. Chengming He, Kuangming Yap, Degang Chen, and R. Geiger, “Nth order circular symmetry pattern and hexagonal tesselation: two new layout techniques cancelling nonlinear gradient.” Proceedings of the 2004 International Symposium on Circuits Systems, May 2004, vol. 1, pp. 237–240.

  7. E. Felt, “Measurement and modeling of MOS transistor current mismatch in analog IC's.” In Proc. of ACM, 1994, pp. 272–277.

  8. A. Hastings, The Art of Analog Layout. Prentice Hall, New Jersey, 2000.

    Google Scholar 

  9. Xin Dai, Chengming He, Hanqing Xing, Degang Chen, and Randall Geiger, “Nth order central symmetrical layout pattern for nonlinear gradient cancellation.” Proceedings of the 2005 International Symposium on Circuits and Systems, May 2005, pp. 4835–4838.

  10. F. Behbahani, Y. Kishigami, J. Leete, and A.A. Abidi, “CMOS mixers and polyphase filters for large image rejection.” IEEE Journal of Solid-State Circuits, vol. 36, pp. 873–887, June 2001.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Chengming He.

Additional information

Chengming He was born in YiWu, China in 1976. He received his B.S. in 1999 in Electronic Engineering department and his M.S. degree in the institute of Microelectronics in 2001 at Tsinghua University, Beijing. He started to work toward his PhD in Iowa State University since August 2001.

Since June 2004 he started to work as a design engineer in Silicon Laboratories, Inc., Austin, TX. He studied and designed LNA, band-pass filter and on-chip power management blocks as well as matching-enhanced layout patterns. He is interested in designing high gain low voltage amplifier, high speed power-efficient ADC and high speed high linear DAC as well as other mixed-signal circuits. He is also interested in the application of nonlinear system dynamical theory in mixed-signal design and yield-enhancement by improving layout matching. He has published more than 10 technical papers. He was a student member of IEEE from 01--04 and now is a member. He is a member of Tau Beta Pi.

Xin Dai was born in Shanghai, China on March 11, 1981. She received the B.Eng. in 2003 from Shanghai Jiao Tong University, Shanghai, China. She is currently a graduate student in Department of Electrical and Computer Engineering at Iowa State University, Ames, IA. Her research has been connected to data converter design and calibrations, layout techniques and build-in-self-test. Xin Dai is now taking a summer-intern in Broadcom Corp., CA.

Hanqing Xing was born in Dalian, China, in 1978. He received the B.S. and M.S. degrees with honors in Electronic Engineering from Tsinghua University, Beijing, China, in 2000 and 2003, respectively. He is currently a PhD student at Iowa State University working in analog and mixed signal design group. His research interests include analog, mixed-signal, and data-conversion integrated circuits design and test.

Degang Chen received his B.S. degree in 1984 in Instrumentation and Automation from Tsinghua University, Beijing, China and his M.S. and Ph.D. degrees in 1988 and 1992, respectively, both in Electrical and Computer Engineering, from the University of California, Santa Barbara.

From 1984 to 1986, he was with the Beijing Institute of Control Engineering, a space industry R/D institute. From March 1992 to August 1992, he was the John R. Pierce Instructor of Electrical Engineering at California Institute of Technology. After that, he joined Iowa State University where he is currently an Associate Professor. He was with the Boeing Company in summer of 1999 and was with Dallas Semiconductor-Maxim in summer of 2001. His research experience include particulate contamination in microelectronic processing systems, vacuum robotics in microelectronics, adaptive and nonlinear control of electromechanical systems, and dynamics and control of atomic force microscopes. His current teaching and research interests are in the area of analog and mixed-signal VLSI integrated circuit design and testing. In particular, he is interested in low-cost high-accuracy testing and built-in-self-test of analog and mixed-signal and RF circuits, and in self-calibration and adaptive reconfiguration/repair strategies for performance and yield enhancement.

Dr. Chen is the recipient of the Best Paper Award at the 1990 IEEE Conference on Decision and Control and the Best Transaction Paper Award from the ASME Journal of Dynamic Systems, Measurement, and Control in 1995. He was selected an A.D. Welliver Faculty Fellow with the Boeing Company in 1999.

Rights and permissions

Reprints and permissions

About this article

Cite this article

He, C., Dai, X., Xing, H. et al. New layout strategies with improved matching performance. Analog Integr Circ Sig Process 49, 281–289 (2006). https://doi.org/10.1007/s10470-006-9705-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-006-9705-1

Keywords

Navigation