Abstract
An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.
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Yu, X.P., Do, M.A., Wu, R. et al. 10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit. Analog Integr Circ Sig Process 45, 191–196 (2005). https://doi.org/10.1007/s10470-005-4012-9
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DOI: https://doi.org/10.1007/s10470-005-4012-9