Abstract
The signal integrity metrics such as jitter, noise, peak-to-peak signal swing and power dissipation play a pivotal role in determining the quality of high data rate on-chip wireline communication and a decision circuit is the most vital section of it. This article explores an area efficient 40 Gb/s configuration of passive element free current mode decision module implemented in 90 nm CMOS technology. The simulation using Cadence Virtuoso platform is carried out at a power supply of 1.2 V along with a clock frequency of 40 GHz and pseudo random bit sequence data input of (27 − 1) having 1 ns bit period. The device foot print of entire arrangement is (76 × 23) µm2, which reads a power dissipation, delay, PDP, peak-to-peak jitter and RMS jitter of 7.02 mW, 198.1 ps, 1.391 pJ, 58.00 ps and 13.12 ps respectively. Monte Carlo runs with ‘no skew’ and 5% process skew are performed at different corners to prove the robustness of the design. The whole circuit is finally validated at lower technology node like 28 nm UMC.
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The authors thankfully acknowledge SMDP-C2SD project under MEITY Govt. of India providing CADENCE tool to carry out this work.
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Maiti, M., Paul, A., Saw, S.K. et al. Passive element free variation aware decision circuit for 40 Gb/s CDR application. Microsyst Technol 26, 1489–1497 (2020). https://doi.org/10.1007/s00542-019-04683-x
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DOI: https://doi.org/10.1007/s00542-019-04683-x