1 Introduction

As the design of integrated circuits (ICs) increase in complexity and scope, the subject of design automation continues to be crucial in not only speeding up the development but also to optimize and verify the functionality of the designs to ensure they meet the required specifications. For the most part, digital circuit designs can be completely automated by describing the behaviour and constraints of the circuit in a highly abstracted hardware description language such as VHDL or System verilog. Analog and mixed-signal (AMS) circuit design automation in contrast still involves a lot of intermediate steps with manual inputs that are necessary to fully develop a complete and functionally verified circuit. This man-in-the-loop approach to analog design is a well-known bottleneck and over the past years a lot of effort has been expended to reduce the level of hands-on by introducing automation concepts in different phases of the analog circuit development flow.

The initial phase of analog circuit design focuses on concept development, where tools like System‑C AMS and MATLAB can be used to model and explore the functional space of the circuit. What follows after that is the mapping of component models to specific architectures which are built from fundamental devices like transistors, resistors and capacitors. Instead of using abstract component models as a first step to verify the model, tools like the hardware description python library (HDL21) [1] present a hardware description language for designing custom digital circuits similar to the programmable approach of digital design. This allows models to encapsulate the constraints (electrical) of specific components based on the process technology required for the design. This also creates an alternative to the traditional GUI schematic approach that is currently standard in the industry with tools like Cadence Virtuoso.

Several design exploration techniques can be used to select the architecture and define the specifications and constraints. In older long-channel process technologies, the square-law equation proves sufficient but is less accurate for short-channel devices and hence the \(\textit{gm}/I_{D}\) method is usually preferred. These techniques lend themselves well to automation as has been shown in [2].

The layout phase of analog design presents the biggest challenge in terms of automation and is usually left to experienced layouter engineers to implement manually. This has meant making last minute changes to the design is usually undesirable for time-sensitive projects. Efforts in tool development to help mitigate this problem include generator-based [3,4,5] and template-based [6] approaches to name a few.

In this paper, we investigate the claim of BAG2 being able to create process-independent analog layouts using parameterized generators, and consider the effort as well as the problems in getting the tool working as required.

The next section describes the details of the BAG2 framework and references some related works of analog circuits implemented with the framework. The benefits are discussed as well as the problems of the current implementation. Section III discusses the setup and configuration of BAG2 for planar process technologies, specifically TSMC 65 nm and GPDK 45 nm. Section IV provides the details of a case study of some analog circuit implementations in the above processes and the efforts as well as the challenges required to get the framework running. The final section discusses the findings from the case study and draws some conclusions on the BAG2 framework.

2 The Berkeley analog generator (BAG2) framework

The BAG2 framework presents a non-traditional approach to analog circuit layout development, in that, it captures the specifications of the circuit into a parameterized generator which can then be executed to automatically generate specific instances of analog circuit layouts. One of the main usefulness of BAG2 is in its process-agnostic approach which allows generators to be used across different process technologies with minimal effort. In this regard, BAG2 has been demonstrated in a lot of published works to show how designs can be ported to different process technologies. [3] shows a differential amplifier for 3 different technologies (GF 45 nm RF SOl, TSMC 28 nm and TSMC 16 nm) using the same generator. In [7], the authors show how circuit layout can be easily iterated depending on specification changes and floor-plan constraints which allows for last minute design changes, which is not usually possible for manually-drawn layouts without considerable effort and time. In [8], the performance of a BAG2-generated layout for a single-tail dynamic comparator is compared to a manually drawn layout and shows similar results which demonstrate the benefits of BAG. Finally in [9], the vanilla BAG2 framework is setup and evaluated to determine the effort required to get it running, for which this work is an extension.

In spite of these benefits, there are still a number of notable limitations with the BAG2 generated circuit layout. Common layout optimization techniques used in analog circuits to reduce device-mismatches such as common-centroid or inter-digitized, as well as guard rings which are used to prevent latch-up currents require considerable effort to implement.

3 BAG2 setup for planar technologies

The promise of the BAG framework is that it enables circuit designers to develop parameterized generators that can be executed to generate layouts for different process technologies. In setting up BAG2 to work with a new process, two problems can be immediately identified. The first is the lack of detailed setup documentation and information channel which makes the setup considerably difficult. The second problem is the lack of sufficient documentation of the application programming interface (API) which is standard and crucial for any software framework. This in addition to the limited source code documentation unnecessarily increases debug time when working with BAG2 and developing generators.

The process-specific parameters are captured in a YAML configuration file. BAG2 comes with a template for planar, fin-FET and SOI processes but only the fin-FET template for the dummy Cadence CDS_FF_MPT 18 nm process is complete.

BAG2 introduces two layout engines that can be used when designing circuit generators. The default XBase layout engine provides some base classes which can be extended to implement the transistor structures for different process technologies. A sample of code structure is shown in Fig. 1. The MOSTechFinfetBase and MOSTechPlanarGeneric classes are extended to implement fin-FET and planar transistors respectively.

Fig. 1
figure 1

BAG2 Code dependency structure

Full size image

Given that TSMC 65 nm and GPDK 45 nm are planar processes, our initial setup extended the transistor base from the MOSTechPlanarGeneric class which provides already defined functions for drawing and routing transistors. Unfortunately, the MOSTechPlanarGeneric class appears incomplete and hence would not run. Upon debugging and trying to fix the code, other problems like missing functions and configurations parameters meant the generated layout had mismatches in device widths, via metal widths, and TAP spacing and hence did not pass DRCs. Fig. 2 shows the layout generated.

Fig. 2
figure 2

BAG2 Planar MOS layout for TSMC 65 nm

Full size image

Since there was no readily available working planar MOS template released with BAG2, the other option was to adapt the available dummy Cadence 18 nm finFET CDS_FF_MPT process template for the planar technologies.

The other layout engine released for BAG2 is LAYGO [10] which offers a different approach to generating circuit layouts. The details and limitations of LAYGO are not discussed in this paper as the focus is on the default XBase engine.

4 Case study

To demonstrate the viability of BAG2 and evaluate its process-independent layout generation claims, two generators were developed and executed for two different process technologies being TSMC 65 nm and Cadence dummy GPDK 45 nm. The generators were also executed on the dummy Cadence fin-FET process (CDS_FF_MPT) for completeness.

4.1 Differential amplifier

Differential amplifiers are used extensively in analog and mixed-signal circuit designs. The specific architecture used is usually determined by the requirements and constraints of the design. For this demonstration, a minimal-effort architecture was chosen which is a differential input and output with NMOS input and tail transistors and PMOS active loads. The supply voltage is 1.2 V as required for the model of transistor used. The dimensioning of the circuit was achieved with the gm/Id methodology.

The specifications for the differential amplifier are summarized in the table below.

Table 1 Differential amplifier specs
Full size table

With the specifications defined, a schematic template was implemented with arbitrary device dimensions. The real values are passed from the layout generator using the layout-first approach of BAG2. The schematic for the differential amplifier as generated by BAG2 is shown in Fig. 3 below.

Fig. 3
figure 3

Differential Amplifier Schematic

Full size image

The layout generator was designed with TSMC 65 nm as the reference process. This meant the routing grid was tailored to the minimum metal spacing and areas of this process. The tracks for routing the transistors were also based on this reference. Fig. 4 shows the generated layout for the TSMC 65 nm process.

Fig. 4
figure 4

Differential Amplifier layout for TSMC 65 nm

Full size image

In the case of GPDK 45 nm which is a smaller node, the same routing grid, the number of tracks as well as transistor dimensions were used to maintain consistency. In order to take advantage on the smaller process, the design will have to be resized and the generator updated to use a different routing grid and number of tracks. Fig. 5 shows the generated layout for the GPDK 45 nm process. The difference in width compared to the TSMC 65 nm process is due to the difference in technology configuration for both processes. Once again, by optimizing the configuration, the GPDK 45 nm should be able to achieve smaller width and hence area.

Fig. 5
figure 5

Differential Amplifier layout for GPDK 45 nm

Full size image

4.2 Common-mode feedback circuit

Another circuit which is used to stabilize the output common-mode voltage of amplifiers is the common-mode feedback circuit (CMFB). The common-mode voltage in this case is set to half the supply voltage which is 0.6 V

The schematic template for the CMFB circuit was first developed with arbitrary transistor dimensions and then the real dimensions were calculated from the generated layout. The schematic as generated by BAG2 is shown in Fig. 6 below.

Fig. 6
figure 6

Common-mode Feedback Circuit Schematic

Full size image

The layout generator for the CMFB circuit was designed for the TSMC 65 nm process with the same routing grid as for the differential amplifier with a suitable floor-plan taking into account the number of devices in the circuit and their interconnections. Fig. 7 shows the generated layout.

Fig. 7
figure 7

Common-mode Feedback Circuit layout for TSMC 65 nm

Full size image

The final step was to also run the generator on the GPDK 45 nm process with the same routing grid, number of routing tracks and the layout as generated is shown in Fig. 8 below.

Fig. 8
figure 8

Common-mode Feedback Circuit layout for GPDK 45 nm

Full size image

5 Generator design and evaluation

5.1 Generator design

Traditionally, layout engineers entirely depend on a visual environment to develop analog circuit layouts. Tools like the Cadence Virtuoso Layout Editor or open-source alternatives like KLayout [12] and MAGICAL [11] allow designers to create and modify device instances to create a layout floor-plan that is consistent to their implementation requirements while being considerate of how the devices are routed by signal and power wires to minimise the impact of parasitic capacitance and device mis-matches.

In the case of BAG2 which is entirely a code-based approach to layout development, designers don’t have direct feedback path to visualising the final layout of the circuit but instead have to rely on an initial draft floor-plan that is implemented by either paper and pencil or some other digital drawing application. This drawback can be significant in the case of complex circuits where the parameters such as number and width of transistor fingers can dramatically change the resulting layout that is generated by the code. Also, the de-coupling of floor-plan draft makes it a bit more difficult for layouters without programming experience to run the generator without additional and sufficient documentation of the code.

From the common-mode feedback circuit shown in Fig. 6, the parameters of the transistors used to achieve the required performance is shown in Table 2. The pair of values in the finger width and number of fingers columns are used to generate 2 different layouts for the CMFB circuit, the details of which are discussed next.

Table 2 CMFB circuit transistor parameters
Full size table

Stacking transistors M3, M4, M1, M2 and M5 into a single column and 5 rows with each transistor having 10 number of fingers and a corresponding finger width for the desired total width as specified in Table 2 results in a balanced layout as shown in Fig. 9.

Fig. 9
figure 9

CMFB Layout with number of fingers \(=10\)

Full size image

On the other hand, opting for more number of fingers, in this case 16 and a corresponding finger width produces a more wider layout that might be necessary if the physical chip structure requires this floor-plan. In either case, the number of dummy transistors that are used to separate the transistors as well as to pad the edges can also change how the final floor-plan of the layout turns out as shown in Fig. 10.

Fig. 10
figure 10

CMFB Layout with number of fingers \(=16\)

Full size image

A third option will be to either arrange the devices into a single row of PMOS transistors stacked on top of a row of NMOS transistors to get an extremely horizontal layout or stack each device on top of each other to get vertical layout but this is considered impractical and is therefore not implemented in this research.

Given the massive design space that has to be explored to achieve the optimum layout, having to write a different generator for every instance of a particular layout floor-plan is not trivial and even though the code can be generalised to some extent to account for a set of layout types, the effort needed to do that might be too significant.

5.2 Hierarchical circuits: differential amplifier with CMFB

BAG2 generators can be instantiated in top-level generators to create a system hierarchy. The each sub-module in a block can be connected to every other sub-module at the same level to achieve the integration that is typically done by hand except in this case the module are connected using code.

Using the 2 different CMFB layout floor-plans, the top-level differential amplifier with CMFB circuit are show in Figs. 11 and 12 which are implemented using two different generators for the CMFB circuit.

It should be noted that the floorplan optimization is also applied to the differential amplifier as well but this has a less significant effect in this case since the CMFB circuit is much bigger and has more devices. For any generator circuit, all the inidividual blocks will have to be optimized to achieve the best top-level layout.

Fig. 11
figure 11

Hierarchical Circuit Floor-plan 1

Full size image
Fig. 12
figure 12

Hierarchical Circuit Floor-plan 2

Full size image

6 Evaluation and discussion

6.1 Evaluation

The verification of analog circuit layout requires the use of tools like Cadence Assura or Siemens Calibre to perform design-rule checks (DRC) and layout-vs-schematic (LVS) to ensure the designs layout matches the schematic netlist as well as meets the requirements as specified in the process development kit (PDK) by the foundry. In addition, the performance of the layout can be evaluated by parasitic extraction (PEX) and compared with the schematic which serves as an ideal target.

In this case, the DC and AC performance of the circuit was evaluated to ensure they met the specification for gain, output common-mode voltage and gain-bandwidth using both parametric simulation of the device over all corners for process-temperature-voltage variation as well as Monte-Carlo.

6.1.1 Hierarchical circuit floor-plan 1 (FP 1)

As can be seen from the results of Monte-Carlo simulation in Figs. 13 and 14, the variation between the schematic and PEX layout using the floor-plan in Fig. 11 is minimal which is primarily a result of using less number of fingers and hence wider finger widths which makes it more tolerant to process variations.

Fig. 13
figure 13

Monte-Carlo Gain using Schematic of Floor-plan 1

Full size image
Fig. 14
figure 14

Monte-Carlo Gain using PEX of Floor-plan 1

Full size image

The same is true for the parametric simulation for the device corners over temperature which can be seen in Figs. 15 and 16. Here the temperature is swept between \(-30\) \({}^{\circ}\)C and 80 \({}^{\circ}\)C.

Fig. 15
figure 15

Parametric Simulation of Gain (dB) for Floor-plan 1 Schematic. Legend: red FF Corner, cyan FS Corner, violet SF Corner, yellow SS Corner, green TT

Full size image
Fig. 16
figure 16

Parametric Simulation of Gain (dB) for Floor-plan 1 PEX Layout. Legend: red FF Corner, green FS Corner, cyan SF Corner, yellow SS Corner, violet TT

Full size image

6.1.2 Hierarchical circuit floor-plan 2 (FP 2)

When using more number of fingers and hence a thinner finger width as is the case for the floor-plan in Fig. 12, the variation in the Monte-Carlo simulation of the gain between the schematic (mean: 36.1045) and PEX layout (mean: 35.8463) is more pronounced which is primarily attributable to effects caused by process variations.

Fig. 17
figure 17

Monte-Carlo Gain using Schematic of Floor-plan 2

Full size image
Fig. 18
figure 18

Monte-Carlo Gain using PEX of Floor-plan 2

Full size image

The parametric simulation once again shows a noticeable variation in the gain performance of the circuit between the schematic (36.91 for best case and 36.31 for worst case) and the PEX layout (36.64 for best case and 35.85 for worst case) over the given temperature range which demonstrates how the choice of floor-plan variables can affect the performance of the circuit as shown in Figs. 19 and 20.

Fig. 19
figure 19

Parametric Simulation of Gain (dB) for Floor-plan 2 Schematic. Legend: red FF Corner, green FS Corner, blue SF Corner, yellow SS Corner, violet TT

Full size image
Fig. 20
figure 20

Parametric Simulation of Gain (dB) for Floor-plan 2 PEX Layout. Legend: red FF Corner, green FS Corner, blue SF Corner, yellow SS Corner, violet TT

Full size image

The results of the parametric simulation for the device corners over temperature is shown in full in the appendix. For much more complex circuits with stringent performance requirements, this variation will be significant and will require more consideration when developing a generator to get the best outcome.

6.2 Discussion

The promise of BAG2 as a process-independent framework for automating analog layouts for the most part works as intended but with significant hurdles that have to be overcome to setup the framework for a new process technology. The most notable problem is the lack of appropriate documentation of the API and source code. This makes it close to impossible to determine and even utilize all the features of the framework. BAG2 releases with a number of tutorial generators and some basic work-flow with minimal documentation and this means generator development has to be tailored to these sample generators which increases the effort for writing more complex generators. Also the effort of debugging and tracing code execution paths is significant, especially when setting up BAG2 for a new process due to the lack of documentation. In this instance, it took about 3 months to fully adapt and setup BAG2 for the TSMC 65 nm process and another 2 weeks to get it to work for the GPDK 45 nm process. The generator code on the other hand took about a month to develop, with a few more days needed to iterate the layout floor-plan.

Once these hurdles are overcome though, generators largely works across multiple processes as shown in this case study.

In order for BAG2 generators to take advantage of any specific process, the generator code requires modification due to differences in the routing grid and number of tracks as a result of different wire lengths/spacing for each process. This inconvenience, though minor is necessary to prevent shorting wires in the circuit and generating DRC-clean layouts.

Lastly, lack of important layout structures like device interleaving to reduce mismatch and guard rings prevents the generated layouts from being optimal.

7 Conclusion and outlook

In effect, this paper evaluates the use of BAG2 as a reliable tool for automating analog layouts for different processes namely the TSMC 65 nm and GPDK 45 nm and shows that it offers a lot of benefits. A case study of a number of analog circuits is used to evaluate the framework.

As noted, the lack of flexibility in using the BAG2 frameworks coupled with the strictly code-based development environment poses a significant hurdle that needs to be overcome by layout engineers to use the framework. The need to develop multiple generators for similar layouts is also inconvenient and increases the initial time and effort which has to be invested do produce a viable layout.

As a next step, the BAG2 generated layout could be compared to a hand-made layout and their performance examined to determine how much of an advantage or disadvantage each solution offers. A more objective analysis would require both the automatic and hand-made layouts implemented on a physical chip which will provide a much more useful insight and would capture the real effect of the process variations and its impact the chip.