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Single-Ended 10T SRAM Cell with High Yield and Low Standby Power

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Abstract

This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates the problem. To evaluate read, write, and hold yields, we performed 10,000 Monto Carlo simulations in the 32-nm technology, and the results show our cell has 7.5×, 1.4×, and 1.1 × more yields than that of the conventional 6T SRAM cell. The proposed cell also has the least static power consumption. This amount is 1.5× less than the conventional 6T at the supply voltage of 0.5 V.

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Data Availability Statement

This manuscript has no associated data or the data will not be deposited. [Authors’ comment: All data generated or analyzed during this study are included in this published article.]

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Erfan Shakouri, Behzad Ebrahimi, Nima Eslami & Mohammad Chahardori

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  1. Erfan Shakouri
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  2. Behzad Ebrahimi
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Correspondence to Behzad Ebrahimi.

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Shakouri, E., Ebrahimi, B., Eslami, N. et al. Single-Ended 10T SRAM Cell with High Yield and Low Standby Power. Circuits Syst Signal Process 40, 3479–3499 (2021). https://doi.org/10.1007/s00034-020-01636-y

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