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10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design

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Abstract

In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.

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References

  1. A. Abumurad, K. Choi, Design procedure and selection of TIQ comparators for flash ADCs. Springer CSSP Process 34(574), 1–36 (2017)

    MATH  Google Scholar 

  2. A. Abumurad, K. Choi, Increasing the ADC precision with oversampling in a flash ADC, in IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (2012)

  3. A.M.A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Bhoraskar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Littimore, J. Bray, C. Speir, R. Sneed, A 16-Bit 250-Ms/s IF sampling pipelined ADC with background calibration. IEEE J. Solid-State Circuit 45(12), 2602–2612 (2010)

    Article  Google Scholar 

  4. M. Ayesh, S. Ibrahim, M. Aboudina, Article title goes here, in International Midwest Symposium on Circuits and Systems (2015)

  5. S. Banik, D. Gangopadhyay, T.K. Bhattacharyya, A low power 1.8 V 4-bit 400-MHz flash ADC in 0.18/spl mu/ digital CMOS, in 19th International Conference on VLSI Design held Jointly with 5th International Conference on Embedded Systems Design (VLSID’06) (2006). https://doi.org/10.1109/VLSID.2006.13

  6. M. Chahardori, M. Sharifkhani, S. Sadughi. A low power 1.2 GSps 4-bit flash ADC in 0.18\(\upmu \text{m}\) CMOS, in East–West Design and Test Symposium (2013)

  7. C. Chen, M. Le, K. Kim, A low power 6-bit flash ADC with reference voltage and common-mode calibration, in Symposium on VLSI Circuits Digest of Technical Papers, vol 44, no. 4, pp. 12–13 (2008)

  8. V. Chen, L. Pileggi, An 8.5 mW 5GS/s 6b flash ADC with dynamic offset calibration in 32 nm CMOS SOI, in Symposium on VLSI Circuits (2013)

  9. S.I. Cho, S. Kim, S.I. Lim, K.H. Baek, A 6-bit 2.5 GSample/s flash ADC using immanent C2MOS comparator in 0.18 \(\upmu \)m CMOS, in IEEE International Symposium on Circuits and Systems, pp. 3379–3382 (2007)

  10. S. Chuenarom, S. Maitreechit, P. Roengruen, V. Tipsuwarnpron, Low power current-mode algorithmic ADC in half flash (BCD), in IEEE Asia Pacific Conference on Circuits and Systems (2006)

  11. D. Daly, A. Chandrakasan, A 6b 0.2-to-0.9 V highly digital flash ADC with comparator redundancy, in IEEE International Solid-State Circuits Conference (2008)

  12. H. Dang, M. Sawan, Y. Savaria, A novel approach for implementing ultra-high speed flash ADC using MCML circuits, in IEEE International Symposium on Circuits and Systems, vol 6, pp. 6158–6161 (2005)

  13. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS, in Symposium on VLSI Circuits Digest of Technical Papers, pp. 64–65 (2007)

  14. K. Deguchi, N. Suwa, M. Ito, T. Kumamoto, T. Miki, A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS. IEEE J. Solid-State Circuits 43(10), 2303–2310 (2008)

    Article  Google Scholar 

  15. Q. Diduck, M. Margala, 6-bit low power low area frequency modulation based flash ADC, in International Symposium on Circuits and Systems (2004)

  16. K. El-Gammal, S. Ibrahim, A 24-mW 65-nm CMOS TI-flash ADC for multi-standard serial-link receivers, in International Midwest Symposium on Circuits and Systems (2016)

  17. D. Ferenci, M. Grozing, F. Lang, M. Berroth, A 3 bit 20 GS/s flash ADC in 65 nm low power CMOS technology, in European Microwave Integrated Circuits Conference (2010)

  18. V. Ferragina, N. Ghittori, F. Maloberti, Low-power 6-bit flash ADC for high-speed data converters architectures, in International Symposium on Circuits and Systems (2006)

  19. M. Ghasemzadeh, A. Soltani, A. Akbari, K. Hadidi, A 6-bit 800 MSps flash ADC in 0.35\(\upmu \)m CMOS, in International Conference on Mixed Design of Integrated Circuits and Systems (2015)

  20. G. Huang, P. Lin, A 5-bit 125-MS/s 367-\(\upmu \)W ADC in 65-nm CMOS, in International Midwest Symposium on Circuits and Systems (2012)

  21. C. Huang, Y. Lin, C. Lin, Y. Shyu, S. Chang, A systematic design automation approach for flash ADCs, in International Symposium on Next Generation Electronicsce, pp. 81–84 (2010)

  22. C. Hung, J. Shiu, I. Chen, H. Chen. A 6-bit 1.6 GSps flash ADC in 0.18\(\upmu \)m CMOS with reversed-reference dummy, in IEEE Asian Solid-State Circuits Conference, pp. 335–338 (2006)

  23. Y. Hwang, J. Lin, C. Huang, J. Chen, W. Lee, An efficient power reduction technique for flash ADC, in IEEE International SOC Conference, pp. 43–46 (2007)

  24. Y. Hsieh, Z. Lin, An 8-bit 1.42 GS/s 0.54 mW CMOS flash ADC, in 8th International Conference on Information, Communications and Signal Processing (2011)

  25. A. Ismail, M. Elmasry, A 6-Bit 1.6-GSps low-power wide band flash ADC Converter in 0.13 \(\upmu \)m CMOS Technology. IEEE J. Solid-State Circuits 43(9), 1982–1990 (2008)

    Article  Google Scholar 

  26. T. Ito, T. Itakura, A 3-GS/s 5-bit 36-mW flash ADC in 65-nm CMOS, in IEEE Asian Solid State Circuits Conference (2010)

  27. A. Jayakumar, K. Vishnu, A 7-bit 500-MHz flash ADC, in International Conference on Computational Systems and Communications (2014)

  28. M. Kijima, K. Ito, K. Kamei, S. Tsukamoto A 6b 3GS/s flash ADC with background calibration, in Custom Integrated Circuits Conference (2009)

  29. J. Kim, B. Sung, W. Kim, S. Ryu, A 6-b 4.1-GS/s flash ADC with time-domain latch interpolation in 90-nm CMOS. IEEE J. Solid-State Circuits 48(6), 1429–1441 (2013)

    Article  Google Scholar 

  30. M. Kulkarni, V. Sridhar, G. Kulkarni, 4-bit flash analog to digital converter design using CMOS-LTE Comparator, in IEEE Asia Pacific Conference on Circuits and Systems (2010)

  31. K. Lad, M. Bhat, A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption, in International Conference on Computer Communication and Informatics (2013)

  32. H. Lee, I. Wang, S. Liu, A 7-bit 400 MS/s sub-ranging flash ADC in 0.18 \(\upmu \)m CMOS, in IEEE International SOC Conference, pp. 11–14 (2007)

  33. D. Lee, J. Yoo, K. Choi, Design method and automation of comparator generation for flash A/D converter, in Proceedings of International Symposium on Quality Electronic Design, pp. 138–142 (2002)

  34. J. Lin, B. Haroun, An embedded 0.8 V/480 pW 6b 22 MHz flash ADC in 0.13\(\upmu \)m digital CMOS process using nonlinear double-interpolation technique, in Solid-State Circuits Conference (2002)

  35. Y. Lin, Y. Lien, S. Chang A 0.35–1 V 0.2–3 GS/s 4-bit low-power flash ADC for a solar-powered wireless module, in International Symposium on VLSI Design Automation and Test (2010)

  36. J. Lin, I. Mano, M. Miyahara, A. Matsuzawa, A 0.5 V, 420 MSps, 7-bit flash ADC using all-digital time-domain delay interpolation, in IEEE International Conference on Electron Devices and Solid State Circuit (2012)

  37. J. Ma, S. Sin, U. Seng-Pan, R. Martins, A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB Applications, in International Symposium on Circuits and Systems (2006)

  38. D. Malathi, R. Greeshma, R. Sanjay, B. Venkataramani, A 4 bit medium speed flash ADC using inverter based comparator in 0.18 \(\upmu \)m CMOS, in International Symposium on VLSI Design and Test (2015)

  39. S. Martin, T. Kayiranga, Y. Shi, H. Li, Comparative study of a 100 kW PV WBG inverter using 1200V SiC MOSFET and JFET cascode devices, in IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 399–405 (2018)

  40. Y. Min, A. Abdullah, H. Kim, S. Kim, A 5-bit 500-MS/s time-domain flash ADC in 0.18 \(\upmu \)m CMOS, in International Symposium on Integrated Circuits (2011)

  41. M. Miyahara, J. Lin, K. Yoshihara, A. Matsuzawa, A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit flash ADC, in IEEE Asian Solid State Circuits Conference (2010)

  42. B. Murmann, The race for the extra decibel—a brief review of the current ADC performance trajectories. IEEE Solid-State Circuit Mag. 7, 58–66 (2015)

    Article  Google Scholar 

  43. B. Nasri, S. Sebastian, K. You, R. RanjithKumar, D. Shahrjerdi, A 700 \(\upmu \) W 1 GS/s 4-bit folding-flash ADC in 65nm CMOS for wideband wireless communications, in IEEE International Symposium on Circuits and Systems (2017)

  44. S. Park, Y. Palaskas, A. Ravi, A 4 GSps 4b flash ADC in 0.18 \(\upmu \)m CMOS, in IEEE International Solid-State Circuits Conference (2006)

  45. S. Park, Y. Palaskas, A. Ravi, A 4 GSps 4b flash ADC in 0.18 \(\upmu \)m CMOS. IEEE J. Solid-State Circuits. 42, 1865–1872 (2007)

    Article  Google Scholar 

  46. S. Park, Y. Palaskas, A. Ravi, R. Bishop, M. Flynn, A 3.5 GS/s 5-b flash ADC in 90 nm CMOS, in Custom Integrated Circuits Conference (2006)

  47. C. Paulus, H. Bluthgen, M. Low, E. Sicheneder. A 4 GS/s 6b flash ADC in 0.13 \(\upmu \)m CMOS, in VLSI Circuits (2004)

  48. J. Pernillo, M. Flynn, A 1.5-GS/s flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. IEEE Trans. Circuits Syst II: Express Briefs 58(12), 837–841 (2011)

    Article  Google Scholar 

  49. J. Proesel, G. Keskin, J. Plouchart, L. Pileggi, An 8-bit 1.5 GS/s flash ADC using post-manufacturing statistical selection, in IEEE Custom Integrated Circuits Conference (2010)

  50. J. Proesel, L. Pileggi, A 0.6-to-1 V inverter-based 5-bit flash ADC in 0.09 \(\upmu \)m digital CMOS, in Custom Integrated Circuits Conference (2008)

  51. G. Rajashekar, M. Bhat, Design of resolution adaptive TIQ flash ADC using AMS 0.35 \(\upmu \)m technology, in International Conference on Electronic Design (2008)

  52. C. Sandner, M. Clara, A. Santner, T. Hartig, F. Kuttner, A 6bit, 1.2 GSps low-power flash-ADC in 0.13 \(\upmu \)m digital CMOS, in Design, Automation and Test in Europe (2005)

  53. P. Scholtens, A 2.5 volt 6 bit 600 MSps flash ADC in 0.25 \(\upmu \)m CMOS, in Solid-State Circuits Conference (2000)

  54. P. Scholtens, M. Vertregt, A 6-b 1.6-Gsps flash ADC in 0.18 \(\upmu \)m CMOS using averaging termination. IEEE J. Solid-State Circuits 37(12), 1599–1609 (2012)

    Article  Google Scholar 

  55. L. Shiwen, D. Hua, G. Peng, G. Xiaoyan, C. Zhiming, W. Xinghua, Z. Shunan, Design and implementation of a CMOS 1 Gsps 5bit flash ADC with offset calibration, in IEEE International Conference on and IEEE Cyber, Physical and Social Computing Green Computing and Communications (2013)

  56. Y. Shu, A 6b 3 GS/s 11 mW fully dynamic flash ADC in 40 nm CMOS with reduced number of comparators, in 2012 Symposium on VLSI Circuits (2012)

  57. T. Sundstrom, A. Alvandpour, A 2.5-GS/s 30-mW 4-bit flash ADC in 90 nm CMOS, in NORCHIP (2008)

  58. G. Tretter, M. Khafaji, D. Fritsche, C. Carta, F. Ellinger, Design and characterization of a 3-bit 24-GS/s flash ADC in 28-nm low-power digital CMOS. IEEE Trans. Microw. Theory Tech. 64(4), 1143–1152 (2016)

    Article  Google Scholar 

  59. C. Tsai, K. Hong, Y. Hwang, W. Lee, T. Lee, New power saving design method for CMOS flash ADC, in Midwest Symposium on Circuits and Systems (2004)

  60. H. Tseng, H. Ou, C. Lin, B. Liu, A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach, in International Symposium on Low Power Electronics and Design (2004)

  61. K. Uyttenhove, A. Marques, M. Steyaert, A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction, in Custom Integrated Circuits Conference (2000)

  62. K. Uyttenhove, M. Steyaert, A 1.8 V, 6 bit, 1.3-GHz CMOS flash ADC in 0.25 \(\upmu \)m CMOS, in Solid-State Circuits Conference (2002)

  63. D. Varma, Reduced comparator low power flash ADC using 35 nm CMOS, in International Conference on Electronics Computer Technology (2011)

  64. A. Varzaghani, A. Kasapi, D. Loizos, S. Paik, S. Verma, S. Zogopoulos, S. Sidiropoulos, A 10.3-GS/s 6-bit flash ADC for 10 G ethernet applications. IEEE J. Solid-State Circuits 48(12), 3038–3048 (2013)

    Article  Google Scholar 

  65. B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, G. Plas. A 2.2 mW 5b 1.75 GS/s Folding flash ADC in 90 nm digital CMOS, in IEEE International Solid-State Circuits Conference (2008)

  66. O. Viitala, S. Lindfors, K. Halonen. A 5-bit 1-GS/s Flash-ADC in 0.13-m CMOS using active interpolation, in Proceedings of the 32nd European Solid-State Circuits Conference, pp. 412–415 (2006)

  67. I. Wang, S. Liu, A 4-bit 10 GSample/sec flash ADC with merged interpolation and reference voltage, in IEEE Asian Solid-State Circuits Conference (2008)

  68. H. Wei, U. Chio, Y. Zhu, S. Sin, U. Seng-Pan, R. Martins. A power scalable 6-bit 1.2 GS/s flash ADC with power on/off track-and-hold and preamplifier, in International Symposium on Circuits and Systems (2008)

  69. X. Xiangyan, Z. Xuerong, Y. Fan, R. Junyan, A 100 MS/s 5bit fully digital flash ADC with standard cells, in International Conference on ASIC (2015)

  70. H. Yu, M. Chang, A 1-V 1.25-GS/S 8-bit self-calibrated flash ADC in 90-nm digital CMOS. IEEE Trans. Circuits Syst. II: Express Briefs 55(7), 668–672 (2008)

    Article  Google Scholar 

  71. Y. Zhao, S. Wang, Y. Qin, Z. Hong, A sub-sampling 3-bit 4 GSps flash ADC in 0.13 \(\upmu \)m CMOS, in IEEE International Conference on Solid-State and Integrated Circuit Technology (2010)

  72. S. Zhang, S. Wang, X. Lin, G. Ren, A 6-bit low power flash ADC with a novel bubble error correction used in UWB communication systems, in IEEE International Conference on Electron Devices and Solid-State Circuits (2014)

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  1. School of Electrical Engineering and Computer Science, The Pennsylvania State University, University Park, PA, 16802, USA

    Abdulrahman Abumurad, Ali Ozdemir & Kyusun Choi

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  1. Abdulrahman Abumurad
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Abumurad, A., Ozdemir, A. & Choi, K. 10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design. Circuits Syst Signal Process 38, 4314–4330 (2019). https://doi.org/10.1007/s00034-019-01024-1

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