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A simplified synthesis of transmission lines with a tree structure

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Abstract

The limiting factor for high-performance systems is being set by interconnection delay rather than transistor switching speed. The advances in circuits speed and density are placing increasing demands on the performance of interconnections, for example chip-to-chip interconnection on multichip modules. To address this extremely important and timely research area, we analyze in this paper the circuit property of a generic distributedRLC tree which models interconnections in high-speed IC chips. The presented result can be used to calculate the waveform and delay in anRLC tree. The result on theRLC tree is then extended to the case of a tree consisting of transmission lines. Based on an analytical approach a two-pole circuit approximation is presented to provide a closed form solution. The approximation reveals the relationship between circuit performance and the design parameters which is essential to IC layout designs. A simplified formula is derived to evaluate the performance of VLSI layout.

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Authors and Affiliations

  1. Department of Electrical Engineering, The University of North Carolina at Charlotte, 28223, Charlotte, NC, USA

    D. Zhou, S. Su & F. Tsui

  2. Sun Microsystems, Inc., 2550 Garcia Avenue, 94043-1100, Mountain View, CA, USA

    D. S. Gao

  3. Department of Computer Science, The University of California at Los Angeles, 90024, Los Angeles, CA, USA

    J. S. Cong

Authors
  1. D. Zhou
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  2. S. Su
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  3. F. Tsui
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  4. D. S. Gao
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  5. J. S. Cong
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Additional information

1. Notice that s k is the solution of equation (7).

2. The case of an arbitrary driving functionf(t) can be discussed similarly.

3. When context is clear we will omit the subscript ofγ.

4. This assumption can be satisfied in most practical interconnection design problems.

5. We suppose thatγ keeps the value determined from the single line case.

6. Recall that we have assumed that a step input is applied at the root of the tree.

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Zhou, D., Su, S., Tsui, F. et al. A simplified synthesis of transmission lines with a tree structure. Analog Integr Circ Sig Process 5, 19–30 (1994). https://doi.org/10.1007/BF01673903

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  • DOI: https://doi.org/10.1007/BF01673903

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