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An analysis of interface trap charges to improve the reliability of a charge-plasma-based nanotube tunnel FET

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Abstract

A new heterodielectric shifted-core-gate nanotube tunneling field-effect transistor (HD-SCG-NT-TFET) is proposed with a higher ON-state current and a better subthreshold swing (SS) compared with the conventional core-gate NT-TFET structure. The charge plasma phenomenon is employed to induce charge carriers inside the channel and source region by applying an appropriate metal workfunction. A brief comparative analysis of the influence of the high-K gate dielectric on the interface trap charges (ITCs) and the resulting effect on the performance of the nanotube structures is also presented for different direct-current (DC) parameters. A reliability analysis for the nanotube TFET is presented for the first time to test how efficiently the proposed device follows the original characteristics. To address reliability concerns for low-power applications, the nanotube TFET structures are investigated in terms of their ION, IOFF, subthreshold swing (SS), and ION/IOFF ratio. All of the analyses are performed in the presence of negative, neutral, and positive ITCs.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Raipur, Chhattisgarh, 492010, India

    Anju Gedam, Bibhudendra Acharya & Guru Prasad Mishra

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  1. Anju Gedam
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  2. Bibhudendra Acharya
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  3. Guru Prasad Mishra
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Correspondence to Guru Prasad Mishra.

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Gedam, A., Acharya, B. & Mishra, G.P. An analysis of interface trap charges to improve the reliability of a charge-plasma-based nanotube tunnel FET. J Comput Electron 20, 1157–1168 (2021). https://doi.org/10.1007/s10825-021-01696-6

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