Abstract.
We describe a hybrid formal hardware verification tool that links the HOL interactive proof system and the MDG automated hardware verification tool. It supports a hierarchical verification approach that mirrors the hierarchical structure of designs. We obtain the advantages of both verification paradigms. We illustrate its use by considering a component of a communications chip. Verification with the hybrid tool is significantly faster and more tractable than using either tool alone.
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Published online: 19 November 2002
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Kort, S., Tahar, S. & Curzon, P. Hierarchical formal verification using a hybrid tool . STTT 4, 313–322 (2003). https://doi.org/10.1007/s10009-002-0082-5
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DOI: https://doi.org/10.1007/s10009-002-0082-5