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Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

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Abstract

This paper presents the design and the analysis of power efficient binary content addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell, but the peripheral circuits are realized by using different adiabatic logic structures. In this paper, we propose the design of 3 novel power efficient binary content addressable memory core cells (PEBCAM core cells) using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 \(\times \) 4 were designed and implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiabatic CAM structures. The circuits were designed using 45nm CMOS technology with a sinusoidal power clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.

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  1. Department of Electronics and Communication Engineering, RMK Engineering College, Chennai, 601206, India

    D. Jothi & R. Sivakumar

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Jothi, D., Sivakumar, R. Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells. Circuits Syst Signal Process 37, 1422–1451 (2018). https://doi.org/10.1007/s00034-017-0628-0

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