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Formal specification and verification of VHDL

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Formal Methods in Computer-Aided Design (FMCAD 1996)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1166))

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Abstract

We give an overview of our system for the verification of VHDL designs1, and discuss its rationale. We present a complete example of a simple processor and discuss general methods for specification of state machines and timed and untimed combinational circuits.

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References

  1. Mark Bickford. A Formal Semantics for VHDL and its Use Towards Verifying a Large Design. Technical Report TM-92-0045, ORA Corporation, December 1992.

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  2. David Guaspari, Carla Marceau, and Wolfgang Polak. Formal verification of Ada programs. IEEE Transactions on Software Engineering, 16:1058–1075, September 1990.

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  3. John V. Guttag and James J. Horning. Larch: Languages and Tools for Formal Specification. Springer-Verlag, 1993.

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  4. Carlos Delgado Kloos and Peter T. Breuer (Editors). Formal Semantics for VHDL. Kluwer Academic Publishers, 1995.

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Author information

Authors and Affiliations

  1. Odyssey Research Associates, USA

    Mark Bickford & Damir Jamsek

Authors
  1. Mark Bickford
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  2. Damir Jamsek
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Editor information

Mandayam Srivas Albert Camilleri

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© 1996 Springer-Verlag Berlin Heidelberg

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Bickford, M., Jamsek, D. (1996). Formal specification and verification of VHDL. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031818

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  • DOI: https://doi.org/10.1007/BFb0031818

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-61937-6

  • Online ISBN: 978-3-540-49567-3

  • eBook Packages: Springer Book Archive

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