Abstract
Many applications of Selforganizing Feature Maps (SOFMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOFMs, a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by 5 array. Due to the scalability of the chips a VME-bus board was built with 16 ICs on it. The controller for the VME-bus and the SOFM hardware are realized using FPGAs. The system runs SOFM applications with up to 400 elements in parallel mode (20 by 20 map). Each weight vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning).
Preview
Unable to display preview. Download preview PDF.
References
Kohonen, T.: “Self-Organizing Maps”, Springer-Verlag, Berlin, 1995.
Rüping, S., Rückert, U., Goser, K.: “Hardware Design for S elf organizing Feature Maps with Binary Inputs”, in J. Mira, J. Cabestany, A. Prieto (Eds.): New Trends in Neural Computation, Lecture Notes in Computer Science 686, Springer Verlag, Berlin (1993), pp. 488–493.
Rüping, S., Goser, K., Rückert, U.: “A Chip for Selforganizing Feature Maps”, IEEE MICRO, Vol. 15, No. 3, June 1995,.pp. 57–59.
Rüping, S.: “VLSI-gerechte Umsetzung von selbstorganisierenden Karten und ihre Einbindung in ein Neuro-Fuzzy Analysesystem“, Fortschritt-Berichte VDI, Reihe 9: Elektronik, Düsseldorf: VDI Verlag, 1995.
Rüping, S., Rückert, U.: “A Scalable Processor Array for Self-Organizing Feature Maps“, Fifth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, MicroNeuro'96, February 12–14, 1996, Lausanne, Switzerland, pp. 285–291.
Witkowski, U., Rüping, S., Rückert, U., Schütte, F., Beinecke, S., Grotstollen, H.: “System Identification Using Selforganizing Feature Maps”, submitted to the Fifth International Conference on Artificial Neural Networks. Cambridge, UK, July 1997.
Schütte, F., Beinecke, S., Grotstollen, H., Witkowski, U., Rüping, S., Rückert, U.: “Structure-and Parameter Identification for a Two-Mass-System With Backlash and Friction Using a Self-Organizing Map”, submitted to the European Conference on Power Electronics and Applications, Trondheim, Norway, September 1997.
Rückert, U., “A Hybride Knowledge Processing Architecture“, IEE-Proc. Publication No. 395 “Intelligent Systems Engineering“, Norwich, UK, 1994, pp.372–377.
Rückert, U., “An Associative Memory with Neural Architecture and it's VLSI Implementation“, Los Alamitos: IEEE Computer Society Press, 1991, pp. 212–218.
Porrmann, M., Rückert, U., Marks, K.-M., Landmann, J., “HiBRIC-MEM, A Memory Controller for PowerPC Based Systems“, submitted to Custom Integrated Circuits Conference CICC'97, Santa Clara, CA, May 5–8, 1997.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1997 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Rüping, S., Porrmann, M., Rückert, U. (1997). A high performance SOFM hardware-system. In: Mira, J., Moreno-Díaz, R., Cabestany, J. (eds) Biological and Artificial Computation: From Neuroscience to Technology. IWANN 1997. Lecture Notes in Computer Science, vol 1240. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0032536
Download citation
DOI: https://doi.org/10.1007/BFb0032536
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-63047-0
Online ISBN: 978-3-540-69074-0
eBook Packages: Springer Book Archive