Abstract
Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.
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Abbreviations
- Sj :
-
square root digit of weight 2−j
- S j ε :
-
{−1, 0, 1}
- S[j]:
-
computed square root value as of stepj
- S sj :
-
sign bit in the representation ofS j in sign and magnitude form
- S m j :
-
magnitude bit in the representation ofS j in sign and magnitude form
- w[j]:
-
residual at stepj in two's complement carry-save representation
- a :
-
sum vector in the carry-save representation of 2w[j]
- b :
-
carry vector in the carry-save representation of 2w[j]
- a i :
-
bit of weight 2−i in the sum vector,a
- bi :
-
bit of weight 2−i in the carry vector,b
- T[j]=−S[j − 1]sj − s 2j 2−(j+1) T i :
-
bit of weight 2−i inT
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Louie, M.E., Ercegovac, M.D. A variable-precision square root implementation for field programmable gate arrays. J Supercomput 9, 315–336 (1995). https://doi.org/10.1007/BF01212874
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DOI: https://doi.org/10.1007/BF01212874