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Parallel multipliers with NOR gates based on G-minimum adders

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Abstract

Based on the adders with a minimum number of NOR gates discussed in Ref. 1, parallel multiplers are designed in Ref. 2, using fewer gates, fewer connections, and faster operation than conventional multipliers based on carry-save adders. In this paper, parallel multipliers of NOR gates are designed, by expressing two numbers to be multiplied in the sign and magnitude representation unlike those in Ref. 2. The multipliers in this paper are advantageous over the carry-save adder-type multipliers known to date, in terms of the number of gates and connections.

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Authors and Affiliations

  1. Institute of Nuclear Energy Research, Lung-tan, Taiwan, Republic of China

    Ging-Shung Yu

  2. Department of Computer Science, University of Illinois, 61801, Urbana, Illinois

    Saburo Muroga

Authors
  1. Ging-Shung Yu
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  2. Saburo Muroga
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Additional information

This work is supported in part by the National Science Foundation under Grant No. MCS77-09744 and MCS81-08505.

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Yu, GS., Muroga, S. Parallel multipliers with NOR gates based on G-minimum adders. International Journal of Computer and Information Sciences 13, 111–121 (1984). https://doi.org/10.1007/BF00978712

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  • DOI: https://doi.org/10.1007/BF00978712

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