Abstract
A Dynamic Random Access Memory (DRAM) chip is to be modified to associatively search data in it as it is being refreshed in the chip and to communicate in a linear systolic array. In a preliminary logic design of a (1024×4096) associative memory chip based on a 4 Mbit DRAM, the ∼6 transistors per sense amplifier in a DRAM are expanded by ∼9 transistors per sense amplifier in the modified chip. The chip size is only slightly increased, and it is manufactured using the same processes, in the same plant, as a DRAM chip; thus should cost about the same as a DRAM. A large array of such modified DRAMs could store a terabit database and search all of it every 60 microseconds. Bit pattern searching and search-rewrite algorithms could be economically performed over very large amounts of data. The concepts and the design of the simple modified DRAM will be discussed in the paper.
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Lipovski, G.J. A four megabit Dynamic Systolic Associative Memory chip. J VLSI Sign Process Syst Sign Image Video Technol 4, 37–51 (1992). https://doi.org/10.1007/BF00930617
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DOI: https://doi.org/10.1007/BF00930617