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Power dissipation of VLSI array processing systems

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Abstract

The Power Factor Approximation (PFA) power estimation method is reviewed and applied to VLSI array processing systems. The power dissipation of 1, 2, and 3 dimensional algorithms implemented on linear, hexagonal, and cubic processor arrays is investigated. Closed form equations are developed which show how the overall power dissipation is influenced by an algorithm's size and dimensionality, the target array processor's size and dimensionality, and the adopted partitioning strategy. The power estimation methods developed in this paper can be applied in the early phases of VLSI algorithm/architecture design, selection, and partitionment. The power dissipation of a matrix-matrix multiplication operation is estimated as an example application.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering R-007, University of California San Diego, 92093-0407, La Jolla, CA

    Paul M. Chau & Scott R. Powell

Authors
  1. Paul M. Chau
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  2. Scott R. Powell
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Additional information

This work was supported in part by the Hughes Aircraft Company fellowship program and the NSF initiation grant MIP-99-10437.

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Chau, P.M., Powell, S.R. Power dissipation of VLSI array processing systems. J VLSI Sign Process Syst Sign Image Video Technol 4, 199–212 (1992). https://doi.org/10.1007/BF00925122

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  • DOI: https://doi.org/10.1007/BF00925122

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