Abstract
A modular analog neuro-chip with on-chip learning capability is described. Two popular learning algorithms, error back-propagation and Hebbian learning, are incorporated with adjustable learning parameters. This analog neuro-chip has a fully modular structure for easy multi-chip expansion. The numbers of synapses and neurons can be expanded by simple pin-to-pin connections without additional circuits. For effective learning, the learning rate, sigmoid slope, and ratio of Hebbian learning term to error back-propagation term can be controlled externally by digital signals. The chip is fabricated and successfully trained with gray-scale patterns as well as XOR problem.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Y.K. Choi and S.Y. Lee, “Subthreshold MOS implementation of neural networks with on-chip error back-propagation learning”, in Proc. Int. Joint Conf. Neural Network, pp. 849–852, Nagoya, Japan, 1993.
T.Shima, T.Kimura, Y.Kamatani, T.Itakura, Y.Fujita and T.Iida, “Neuro chips with on-chip back-propagation and/or Hebbian learning”, IEEE J. Solid State Circuits, Vol. 27, pp. 1868–1876, 1992.
S. M.Gowda, B. J.Sheu, J.Choi, C. G.Hwang, J. S.Cable, “Design and characterization of analog VLSI neural network modules”, IEEE J. Solid State Circuits, Vol. 28, pp. 201–313, 1993.
C. Lau, “Neural networks on a chip”, in Proc. World Congress on Neural Network, pp. 1907–1911, Washington DC, USA, 1995.
M. Chiaberge, D. Del Corso, L.M. Reynei and L. Zocca, “A real time controller based on a pulse stream neural system”, in Proc. World Congress on Neural Network, Vol. 2, pp. 147–152, San Diego, USA, 1994.
X. Arreguit, and E. A. Vittoz, “Analog VLSI hardware: what is missing for industrial realisations”, in Proc. Int. Conf. on Neural Network, pp. 1883–1884, Orlando, USA, 1994.
P.H.W. Leong, M. Jabri, “A VLSI neural network for morphology classification”, in Proc. Int. Joint Conf. Neural Network, Vol. 2, pp. 678–683, Baltimore, USA, 1992.
E. Lange, E. Funatsu, K. Hara, K. Kyuma, “Artificial retina devices — fast front ends for neural image processing systems”, in Proc. Int. Joint Conf. Neural Network, pp. 801–804, Nagoya, Japan, 1993.
T. Duong, S. Kemeny, M. Tran, T. Daud, and A. Thakoor, “Low power analog neurosynapse chips for a 3-D sugarcube neuroprocessor”, pp. 1907–1911, in Proc. Int. Conf. on Neural Network, Orlando, USA, 1994.
S. Y. Lee, “Error minimization, generalization, and hardware implementability of supervised learning”, in Proc. World Congress on Neural Network, Vol. 3, pp. 325–330, San Diego, USA, 1994.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Cho, JW. Modular neuro-chip with on-chip learning and adjustable learning parameters. Neural Process Lett 4, 45–52 (1996). https://doi.org/10.1007/BF00454845
Issue Date:
DOI: https://doi.org/10.1007/BF00454845