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Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder

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Intelligent Computing and Communication (ICICC 2022)

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 1447))

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Abstract

In recent times, arithmetic operations involve very small or large numbers. These operations become easy by using floating-point numbers. Generally, the results of these operations are rounded to the nearest value. But while rounding, an error may occur. Half Unit Biased (HUB) representation is useful in avoiding this error. HUB-based numbers are obtained after the represented numbers are shifted by half a unit in the last place. For HUB-based adders, speed is restricted by how the carry propagates throughout the adder. An idea to study the effect of inexact speculative techniques on the speed of floating-point adders is put forth in this paper. Hence, an inexact speculative HUB floating-point adder is proposed. In this adder, carry is propagated in shorter paths rather than the entire architecture of the adder. Thus, the speed of adding two numbers increases when an intermediate carry is estimated by using only a few of the previous stages. In this Paper, the proposed adder has been implemented on Field Programmable Gate Array(FPGA). The speed of the proposed adder has increased by 81.19% compared to conventional 64-bit floating-point adder.

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References

  1. Hormigo J, Villalba J (2016) New formats for computing with real-numbers under round- to-nearest. IEEE Trans Comput 65(7):2158–2168

    Google Scholar 

  2. Ramesh S, Saravanavel K (2021) HUB floating-point adder using double path. Int J Scientif Res Sci Technol (IJSRST) 9(1):708–717

    Google Scholar 

  3. Shaik A, Fairooz SK (2020) HUB floating-point addition using unbiased rounding. IOSR J VLSI and Signal Process (IOSR-JVSP) 10(1):09–14

    Google Scholar 

  4. Lahari M, Agrawal S (2020) Efficient floating-point HUB Adder For FPGA. In: 2020 4th international conference on electronics, materials engineering and nano-technology (IEMENTech), Kolkata, India

    Google Scholar 

  5. Villalba-Moreno J, Hormigo J, González-Navarro S (2018) Unbiased rounding for HUB floating-point addition. IEEE Trans Comput 67(9):1359–1365

    Google Scholar 

  6. Srinivas Reddy T, Shekar CH, Prabhakar J (2019) Analyze and Implementation of FPGA Implementation of HUB floating-point addition. Int J Recent Technol Eng (IJRTE) 7(ICETESM)

    Google Scholar 

  7. Villalba-Moreno J (2016) Digit recurrence floating-point division under HUB format. In: 2016 IEEE 23nd symposium on computer arithmetic (ARITH), Silicon Valley, CA, USA, pp 79–86

    Google Scholar 

  8. Hormigo J, Villalba J (2016) Measuring improvement when using HUB formats to implement floating-point systems under round-to-nearest. IEEE Trans Very Large Scale Integra (VLSI) Syst 24(6):2369–2377

    Google Scholar 

  9. Swetha Bai K, Vijay Murugan S (2020) High speed inexact speculative adder using carry look ahead adder and brent kung adder. Int Res J Eng Technol (IRJET) 7(3):1006–1010

    Google Scholar 

  10. Reethika Rao V, Ragini K (2014) Comparative analysis of 32 bit carry lookahead adder using high speed constant delay logic. Int J Sci Eng Technol Res (IJSETR) 3(10):2768–2774

    Google Scholar 

  11. Shrestha R (2017) High-speed and low-power VLSI-architecture for inexact speculative adder. In: International symposium on VLSI design, automation and test (VLSI-DAT), Hsinchu, Taiwan, 24–27 April

    Google Scholar 

  12. Camus V, Schlachter J, Enz C (2015) Energy-efficient inexact speculative adder with high performance and accuracy control. In: 2015 IEEE international symposium on circuits and systems (ISCAS), Lisbon, Portugal

    Google Scholar 

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, G. Narayanamma Institute of Technology and Science, Hyderabad, Telangana, India

    Vani Dasu & K. Ragini

Authors
  1. Vani Dasu
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  2. K. Ragini
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Corresponding author

Correspondence to Vani Dasu .

Editor information

Editors and Affiliations

  1. Department of Computer Science, G. Narayanamma Institute of Technology and Science (Autonomous), Hyderabad, India

    M. Seetha

  2. Department of Computer Science, Indian Institute of Technology Roorkee, Roorkee, India

    Sateesh K. Peddoju

  3. Faculty of Data Science, San Francisco Bay Area, California, CA, USA

    Vishnu Pendyala

  4. Department of Electronics and Communication Engineering, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    Vedula V. S. S. S. Chakravarthy

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Dasu, V., Ragini, K. (2023). Implementation of 64-Bit Inexact Speculative Half Unit Biased Floating-Point Adder. In: Seetha, M., Peddoju, S.K., Pendyala, V., Chakravarthy, V.V.S.S.S. (eds) Intelligent Computing and Communication. ICICC 2022. Advances in Intelligent Systems and Computing, vol 1447. Springer, Singapore. https://doi.org/10.1007/978-981-99-1588-0_39

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