Abstract
Comparators are used in data converters, sense amplifiers, RFID and data receivers. This paper presents a novel comparator topology for ADC design, in which cascode transistors are stacked on the top of differential input section. In terms of speed, offset voltage, power dissipation and kickback noise, this design improves the comparator’s overall performance. The design and simulations are carried out on standard UMC 180 nm technology, for 100 MHz clock, at 1.8 V supply using Cadence Virtuoso EDA tool for the sake of reasonable comparison.
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References
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Bandla, K., Dinakar, A., Pal, D. (2023). A Novel Dynamic Latch Comparator Design and Analysis for ADCs. In: Seetha, M., Peddoju, S.K., Pendyala, V., Chakravarthy, V.V.S.S.S. (eds) Intelligent Computing and Communication. ICICC 2022. Advances in Intelligent Systems and Computing, vol 1447. Springer, Singapore. https://doi.org/10.1007/978-981-99-1588-0_11
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DOI: https://doi.org/10.1007/978-981-99-1588-0_11
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