Abstract
An implementation of frequency divider circuit as an application of D flip flop using CMOS technique on cadence virtuoso 16.1 gpdk model library has been reported in this paper. Circuit performance and stability have been improved by using a dynamic signal driving strategy that maintains minimum power consumption with 0.8 V supply voltage and 90 nm process technology. A very low number of components are used which will helps to provide minimum area consumption. The average power of the proposed circuit is 15.43 μW, and PDP is 0.079 fj. At room temperature, average power consumption with respect to technology and voltage for various reported circuits as well as for the proposed circuit has been analyzed and has been found that the proposed circuit consumes 99.48, 98.457, 99.228, 98.457 and 92.285% less power than the circuits reported in the literature.
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© 2023 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
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Pandey, P., Kumar, A., Singh, R.K. (2023). Design and Analysis of Low Power Frequency Divider Circuit. In: Nagaria, R.K., Tripathi, V.S., Zamarreno, C.R., Prajapati, Y.K. (eds) VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore. https://doi.org/10.1007/978-981-99-0973-5_12
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DOI: https://doi.org/10.1007/978-981-99-0973-5_12
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